Buffer circuits

专利名称：Buffer circuits发明人：Hiroaki, Ikeda申请号：EP83101022申请日：19830203公开号：EP00836A3公开日：19860205

专利附图：

摘要：In a buffer circuit for producing to output signals (A,) of the opposite phases inresponse to an input signal (A) comprising a pre-circuit (1) producing two pre-outputsignals (A', ') in accordance with the input signal (A) and a reference voltage signal (V); anda main circuit (2) including a latch circuit (Q, Q) latching the pre-output signals (A', '), and a

flip-flop circuit (Q, Q) connected to receive the pre-output signals (A', ') latched by thelatch circuit (Q, Q) for producing the output signals (A,) of the buffer circuit, there isprovided a transfer gate circuit (Q, Q,, Q, Q, C, C) enabled by the pre-output signals (A', ')and disabled by the output signals (A, ) of the buffer circuit. According to this invention,different from the prior art circuit, it is not necessary to use any clock signal having a highlevel at the time of operation of the buffer circuit and to have strict time spacing,whereby the clock signal generator can be simplified and the buffer circuit can beminiaturized and its operatin speed can be increased (Figure 3).

申请人：NEC CORPORATION

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