CMOS power-up reset circuit for gate arrays and st

专利名称：CMOS power-up reset circuit for gate arrays

and standard cells

发明人：Steven R. Norsworthy申请号：US06/673386申请日：19841120公开号：US04633107A公开日：19861230

摘要：A power-up reset circuit has a first circuit for sensing a source voltage potentialand generating a reset signal at an output when the source voltage potential rises abovea threshold level. An input of the sensing circuit is coupled to the source voltagepotential to permit a voltage at the sensing circuit's input to follow the source voltagepotential during an initial rise of the source voltage potential. The power-up reset circuitfurther has a second circuit for sensing the source voltage potential and generating atime delayed signal at an output when the source voltage potential rises above apredetermined level. A termination circuit has an input coupled to the output of thesecond circuit and generates a termination signal at an output coupled to the input ofthe first circuit to terminate the reset signal in response to the time delayed signal. Afeedback switch has an input coupled to the output of the first circuit and couples theterminating circuit to the source voltage potential in response to the reset signal anddecouples the terminating circuit from the source voltage potential in response to thetermination of the reset signal.

申请人：HARRIS CORPORATION

代理机构：Barnes & Thornburg

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