ADC08D1520QML

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ADC08D1520QML Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D ConverterJune 8, 2009

ADC08D1520QML

Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/DConverter

General Description

The ADC08D1520 is an 8–Bit, dual channel, low power, highperformance CMOS analog-to-digital converter that buildsupon the ADC08D1000 platform. The ADC08D1520 digitizessignals to 8 bits of resolution at sample rates up to 1.7 GSPS.It has expanded features compared to the ADC08D1000,which include a test pattern output for system debug, clockphase adjust, and selectable output demultiplexer modes.Consuming a typical 2.0W in Demultiplex Mode at 1.5 GSPSfrom a single 1.9 Volt supply, this device is guaranteed to haveno missing codes over the full operating temperature range.The unique folding and interpolating architecture, the fully dif-ferential comparator design, the innovative design of the in-ternal sample-and-hold amplifier and the self-calibrationscheme enable a very flat response of all dynamic parametersbeyond Nyquist, producing a high 7.2 Effective Number of Bits(ENOB) with a 748 MHz input signal and a 1.5 GHz samplerate while providing a 10-18 Code Error Rate (C.E.R.) Outputformatting is offset binary and the Low Voltage DifferentialSignaling (LVDS) digital outputs are compatible with IEEE1596.3-1996, with the exception of an adjustable commonmode voltage between 0.8V and 1.2V.

Each converter has a selectable output demultiplexer whichfeeds two LVDS buses. If the 1:2 Demultiplexed Mode is se-lected, the output data rate is reduced to half the input samplerate on each bus. When Non-Demultiplexed Mode is select-ed, that output data rate on channels DI and DQ are at thesame rate as the input sample clock. The two converters canbe interleaved and used as a single 3 GSPS ADC.

The converter typically consumes less than 2.9 mW in thePower Down Mode and is available in a 128-pin, thermallyenhanced, multi-layer ceramic quad package and operatesover the Military (-55°C ≤ TA ≤ +125°C) temperature range.

Features

■■■■■■■■■■■■

Total Ionizing Dose300 krad(Si)Single Event Latch-up120 MeV-cm2/mgSingle +1.9V ±0.1V Operation

Interleave Mode for 2x Sample RateMultiple ADC Synchronization Capability

Adjustment of Input Full-Scale Range, Offset and ClockPhase Adjustment

Choice of SDR or DDR output clocking1:1 or 1:2 Selectable Output DemuxSecond DCLK output

Duty Cycle Corrected Sample ClockTest pattern

Serial Interface for Extended Control

Key Specifications

■■■■■■

Resolution

Max Conversion RateCode Error Rate

ENOB @ 748 MHz InputDNL

Power Consumption

—Operating in 1:2 Demux Output—Power Down Mode

8 Bits

1.5 GSPS (min)

10-18 (typ)7.2 Bits (typ)±0.15 LSB (typ)2.0 W (typ)2.9 mW (typ)

Applications

■■■■

Direct RF Down ConversionDigital Oscilloscopes

Communications SystemsTest Instrumentation

Ordering Information

NS Part NumberADC08D1520WGFQV

SMD Part Number5962F0721401VZC

300 krad(Si)

NS Package Number

EM128A

Package Discription128L, CERQUADGULLWING

ADC08D1520QMLBlock Diagram

30024753

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ADC08D1520QMLPin Configuration

30024701

Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance.

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ADC08D1520QMLPin Descriptions and Equivalent Circuits

Pin FunctionsPin No.

Symbol

Equivalent Circuit

Description

Output Voltage Amplitude and Serial Interface Clock. Tie thispin high for normal differential DCLK and data amplitude.Ground this pin for a reduced differential output amplitudeand reduced power consumption. See 1.1.6 The LVDSOutputs. When the extended control mode is enabled, thispin functions as the SCLK input which clocks in the serialdata. See 1.2 NON-EXTENDED CONTROL/EXTENDEDCONTROL for details on the extended control mode. See1.3 THE SERIAL INTERFACE for description of the serialinterface.

A logic high on the PDQ pin puts only the Q-Channel ADCinto the Power Down mode.

DCLK Edge Select, Double Data Rate Enable and SerialData Input. This input sets the output edge of DCLK+ atwhich the output data transitions. See 1.1.5.2 OutEdge andDemultiplex Control Setting When this pin is connected to1/2 the supply voltage,VA/2, DDR clocking is enabled. Whenthe Extended Control Mode is enabled, this pin functions asthe SDATA input. See 1.2 NON-EXTENDED CONTROL/EXTENDED CONTROL for details on the Extended ControlMode. See 1.3 THE SERIAL INTERFACE for description ofthe serial interface.

DCLK Reset. When single-ended DCLK_RST is selected bysetting pin 52 logic high or to VA/2, a positive pulse on thispin is used to reset and synchronize the DCLK outputs ofmultiple converters. See 1.5 MULTIPLE ADC

SYNCHRONIZATION for detailed description. When

differential DCLK_RST is selected by setting pin 52 logic low,this pin receives the positive polarity of a differential pulsesignal used to reset and synchronize the DCLK outputs ofmultiple converters.

Power Down Pins. A logic high on the PD pin puts the entiredevice into the Power Down Mode.

Calibration Cycle Initiate. A minimum tCAL_L input clock

cycles logic low followed by a minimum of tCAL_H input clockcycles high on this pin initiates the calibration sequence. See2.5.2 Calibration for an overview of calibration and 2.5.2.1Initiating Calibration for a description of calibration.Full Scale Range Select, Alternate Extended Control Enableand DCLK_RST-. This pin has two functions. It can

conditionally control the ADC full-scale voltage, or becomethe negative polarity signal of a differential pair in differentialDCLK_RST Mode. If pin 52 and pin 41 are connected at logichigh, this pin can be used to set the full-scale-range. Whenused as the FSR pin, a logic low on this pin sets the full-scaledifferential input range to a reduced VIN input level. A logichigh on this pin sets the full-scale differential input range toHigher VIN input level. See Converter Electrical

Characteristics. When pin 52 is held at logic low, this pin actsas the DCLK_RST- pin. When in differential DCLK_RSTMode, there is no pin-controlled FSR and the full-scale-rangeis defaulted to the higher VIN input level.

3OutV / SCLK

29PDQ

OutEdge / DDR /

SDATA

DCLK_RST/DCLK_RST+

26PD

30CAL

14FSR/DCLK_RST-

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ADC08D1520QMLPin FunctionsPin No.

Symbol

Equivalent Circuit

Description

Dual Edge Sampling and Serial Interface Chip Select. Withpin 41 logic low, the device is in Extended Control Mode andthis pin is the enable pin for the Serial Interface . When inNon-Extended Control Mode and this pin is connected toVA/2, DES Mode is selected where the I- Channel input issampled at twice the input clock rate and the Q- Channelinput is ignored. See 1.1.5.1 Dual-Edge Sampling. When inNon-Extended Controll Mode and DES is not desired, thispin should be tied to VA.

127DES / SCS1819CLK+CLK-

LVDS Clock input pins for the ADC. The differential clocksignal must be a.c. coupled to these pins. The input signal issampled on the falling edge of CLK+. See 1.1.2 Acquiringthe Input for a description of acquiring the input and 2.4 THECLOCK INPUTS for an overview of the clock inputs.

1011.2223

VINI−VINI+VINQ+VINQ−

Analog signal inputs to the ADC. These differential inputsignals must be a.c. coupled to these pins. The differentialfull-scale input range is programmable using the FSR pin 14in Non-Extended Control Mode and the Input Full-ScaleVoltage Adjust register in the Extended Control Mode. Referto the VIN specification in the Converter Electrical

Characteristics for the full-scale input range in the Non-Extended Control Mode. Refer to 1.4 REGISTER

DESCRIPTION for the full-scale input range in the ExtendedControl Mode.

Bandgap output voltage. This pin is capable of sourcing orsinking 100 μA and can drive a load up to 80 pF.

VBG

126CalRun

Calibration Running indication. This pin is at a logic highwhen calibration is running.

REXT

External bias resistor connection. Nominal value is 3.3 kΩ(±0.1%) to ground. See 1.1.1 Calibration.

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ADC08D1520QMLPin FunctionsPin No.3435

SymbolTdiode_PTdiode_N

Equivalent Circuit

Description

Temperature Diode Positive (Anode and Negative(Cathode). This pin is used for die temperaturemeasurements. See 2.7.2 Thermal Management.

41ECEExtended Control Enable. This pin always enables or

disables Extended Control Mode. When this pin is set logichigh, the Extended Control Mode is inactive and all controlof the device must be through control pins only . When it isset logic low, the Extended Control Mode is active. This pinoverrides the Extended Control Enable signal set using pin14.

52DRST_SEL

DCLK_RST select. This pin selects whether the DCLK isreset using a single-ended or differential signal. When thispin is connected at logic high, the DCLK_RST operation issingle-ended and pin 14 functions as FSR/ALT_ECE. Whenthis pin is logic low, the DCLK_RST operation becomesdifferential with functionality on pin 15 (DCLK_RST+) and pin14 (DCLK_RST-). When in differential DCLK_RST Mode,there is no pin-controlled FSR and the full-scale-range isdefaulted to 870mV. When pin 41 is set logic low, the

Extended Control Mode is active and the Full-Scale VoltageAdjust registers can be programmed.

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ADC08D1520QMLPin FunctionsPin No.83 / 7884 / 7785 / 7686 / 75 / 7290 / 7191 / 7092 / 6993 / / 6795 / 6696 / 65100 / 61101 / 60102 / 59103 / 58104 / 57105 / 56106 / 55107 / 111 / 50112 / 49113 / 48114 / 47115 / 46116 / 45117 / 44118 / 43122 / 39123 / 38124 / 37125 / 36

SymbolDI7− / DQ7−DI7+ / DQ7+DI6− / DQ6−DI6+ / DQ6+DI5− / DQ5−DI5+ / DQ5+DI4− / DQ4−DI4+ / DQ4+DI3− / DQ3−DI3+ / DQ3+DI2− / DQ2−DI2+ / DQ2+DI1− / DQ1−DI1+ / DQ1+DI0− / DQ0−DI0+ / DQ0+DId7− / DQd7−DId7+ / DQd7+DId6− / DQd6−DId6+ / DQd6+DId5− / DQd5−DId5+ / DQd5+DId4− / DQd4−DId4+ / DQd4+DId3− / DQd3−DId3+ / DQd3+DId2− / DQd2−DId2+ / DQd2+DId1− / DQd1−DId1+ / DQd1+DId0− / DQd0−DId0+ / DQd0+

Equivalent Circuit

Description

I- and Q- channel LVDS Data Outputs that are not delayedin the output demultiplexer. Compared with the DId and DQdoutputs, these outputs represent the later time samples.These outputs should always be terminated with a 100Ωdifferential resistor.

I- and Q- channel LVDS Data Outputs that are delayed byone CLK cycle in the output demultiplexer. Compared withthe DI and DQ outputs, these outputs represent the earliertime sample. These outputs should always be terminatedwith a 100Ω differential resistor. In Non Demux Mode, theseoutputs are disabled and are high impedance. Whendisabled, these outputs must be left floating.

7980OR+/DCLK2+OR-/DCLK2-

Out Of Range output. A differential high at these pins

indicates that the differential input is out of range ±VIN/2 asprogrammed by the FSR pin in Non-Extended Control Modeor the Input Full-Scale Voltage Adjust register setting in theExtended Control Mode). DCLK2 is the exact mirror of DCLKand should output the same signal at the same rate.Data Clock. Differential Clock outputs used to latch theoutput data. Delayed and non-delayed data outputs aresupplied synchronous to this signal. In 1:2 DemultiplexedMode, this signal is at 1/2 the input clock rate in SDR Modeand at 1/4 the input clock rate in the DDR Mode. By default,the DCLK outputs are not active during the terminationresistor trim section of the calibration cycle. If a systemrequires DCLK to run continuously during a calibration cycle,the termination resistor trim portion of the cycle can bedisabled by setting the Resistor Trim Disable (RTD) bit tologic high in the Extended Configuration Register (address9h). This disables all subsequent termination resistor trimsafter the initial trim which occurs during the power on

calibration. Therefore, this output is not recommended as asystem clock unless the resistor trim is disabled. When thedevice is in the Non-Demultiplexed Mode, DCLK can only bein DDR Mode and the signal is at 1/2 the input clock rate.

8182DCLK-DCLK+

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ADC08D1520QMLPin FunctionsPin No.2, 5, 8, 13,16, 17, 20,25, 28, 33,

12840, 51, 62,73, 88, 99,110, 1211, 6, 7, 9,12, 21, 24,

2742, 53, ,74, 87, 97,108, 11963, 98, 109,

120

Symbol

Equivalent Circuit

Description

Analog power supply pins. Bypass these pins to ground.

VDR

Output Driver power supply pins. Bypass these pins to DRGND.

GND

Ground return for VA.

DR GND

Ground return for VDR.

No Connection. Make no connection to these pins.

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ADC08D1520QMLAbsolute Maximum Ratings

(Notes 1, 2)

Supply Voltage (VA, VDR)Supply Difference VDR - VA

Voltage on Any Input PinVoltage on VIN+, VIN-(Maintaining Common Mode)Ground Difference |GND - DR GND|

Input Current at Any Pin (Note 3)Package Input Current (Note 3)Junction TemperatureESD Susceptibility (Note 4) Human Body ModelStorage Temperature

2.2V

0V to 100 mV

−0.15V to (VA +0.15V)

−0.15V to 2.5V0V to 100 mV

±25 mA±50 mA

Operating Ratings

Ambient Temperature RangeVA/2 Tolerance for supply 1.9VSupply Voltage (VA)

Driver Supply Voltage (VDR)VIN+, VIN- Voltage Range(Maintaining Common Mode)SGround Difference

(|GND - DR GND|)CLK Pins Voltage RangeDifferential CLK Amplitude

(Notes 1, 2)

−55°C ≤ TA ≤ +125°C650mV ≥ VA/2 ≤ 1.2V+1.8V to +2.0V+1.8V to VA0V to 2.15V(100% duty cycle)

0V to 2.5V(10% duty cycle)0V0V to VA

0.4VP-P to 2.0VP-P

≤ 175°C

Class 3A (6000V)−65°C to +175°C

Package Thermal Resistance

Package128L Cer Quad

Gullwing

θJA11.5°C/ W

θJCTop ofPackage3.8°C/ W

θJCThermalPad2.0°C/ W

oldering process must comply with NationalSemiconductor’s Reflow Temperature Profile specifications.Refer to www.national.com/packaging.

Quality Conformance Inspection

MIL-STD-883, Method 5005 - Group A

Subgroup

12345678A8B91011121314

DescriptionStatic tests atStatic tests atStatic tests atDynamic tests atDynamic tests atDynamic tests atFunctional tests atFunctional tests atFunctional tests atSwitching tests atSwitching tests atSwitching tests atSetting time atSetting time atSetting time at

Temp ( C)+25+125-55+25+125-55+25+125-55+25+125-55+25+125-55

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ADC08D1520QMLADC08D1520 Converter Electrical CharacteristicsDC Parameters

(Note 14)

The following specifications apply after calibration for VA = VDR = +1.9V; OutV = 1.9V; VIN FSR (a.c. coupled) = differential 870mVP-P; CL = 10 pF; Differential, a.c. coupled Sine Wave Input Clock, fCLK = 1.5 GHz at 0.5 VP-P with 50% duty cycle; VBG = Floating;Non-Extended Control Mode; SDR Mode; REXT = 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω Differential; 1:2 OutputDemultiplex, duty cycle stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwisenoted. (Notes 5, 6)Symbol

Parameter

Conditions

Notes

Typical(Note 7)

Min

Max

Units

Sub-groups

(Note8)(Note8)

±0.3±0.15 −0.55±45−0.6−1.31±20

−1.5

±.9±.681.5

±25±25

LSBLSBBitsLSBmVmVmV%FS

1, 2, 31, 2, 31, 2, 31, 2, 3 1, 2, 31, 2, 3

(Note9)(Note9)

6009000.021.60.082.2100

94 1.20

ppm/°C

530 840

650 960 106 1.33

mVP-PmVP-PmVP-PmVP-PpFpFpFpFΩΩVV

1, 2, 31, 2, 31, 2, 31, 2, 3 1, 2, 31, 2, 3

1.26

1, 2, 31, 2, 3

STATIC CONVERTER CHARACTERISTICSINLDNL VOFFVOFF_ADJPFSENFSEFS_ADJ

Integral Non-Linearity(Best fit)

Differential Non-Linearity

DC Coupled, 1 MHz Sine WaveOveranged

Resolution with No Missing

CodesOffset Error

Input Offset AdjustmentRange

Positive Full-Scale ErrorNegative Full-Scale ErrorFull-Scale AdjustmentRange

Extended Control Mode

ANALOG INPUT AND REFERENCE CHARACTERISTICS

Full Scale Analog

Differential Input Range

FSR pin 14 LowFSR pin 14 High

VIN

CIN

Analog Input Capacitance,DifferentialNormal operationEach input pin to groundAnalog Input Capacitance,DifferentialDES ModeEach input pin to groundDifferential InputResistanceBandgap ReferenceOutput VoltageBandgap ReferenceVoltage TemperatureCoefficientMaximum BandgapReference loadCapacitanceTemperature DiodeVoltage

RIN

ANALOG OUTPUT CHARACTERISTICSVBGTC VBGCLOADVBG

IBG = ±100 µATA = −55°C to +125°C,IBG = ±100 µA

TEMPERATURE DIODE CHARACTERISTICSΔVBE

192 µA vs 12 µA, TJ = 25°C192 µA vs 12 µA, TJ = 125°C

71.2394.8

mVmV

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ADC08D1520QMLSymbolParameterConditionsNotes

Typical(Note 7)

111< 1−66

MinMaxUnits

Sub-groups

CHANNEL-TO-CHANNEL CHARACTERISTICS X-TALK

Offset Match

Positive Full-Scale MatchNegative Full-Scale MatchPhase Matching (I,Q)

Zero offset selected in ControlRegister

Zero offset selected in ControlRegisterfIN = 1.0 GHz

−66

Sine Wave ClockSquare Wave ClockVIN = 0 or VIN = VADifferential

Each input to ground

(Note9)

0.60.6±10.021.5

0.67 xVA

0.77 xVA

.5 .5

2.0 2.0

VP-PVP-PVP-PVP-PµApFpF

1, 2, 31, 2, 31, 2, 31, 2, 3

LSBLSBLSBDegreedB

Crosstalk from I- ChannelAggressor = 1160 MHz F.S.(Aggressor) to Q- ChannelVictim = 100 MHz F.S.(Victim)

Crosstalk from Q- ChannelAggressor = 1160 MHz F.S.(Aggressor) to I- ChannelVictim = 100 MHz F.S.(Victim)

X-TALK

CLOCK INPUT CHARACTERISTICS

Differential Clock InputLevelInput CurrentInput Capacitance

VID

IICIN

DIGITAL CONTROL PIN CHARACTERISTICSVIHVILVIH

Logic High Input VoltageLogic Low Input VoltageLogic High Input Voltage

OutV, DCLK_RST, PD, PDQ CALOutV, DCLK_RST, PD, PDQ CALOutEdge, FSR, DES/SCSOutEdge, FSR

VIL

Logic Low Input Voltage

DES/SCSCIN

Input Capacitance

Each input to ground

(Note15)(Note11)(Note13)(Note13)

±1

VBG = Floating (See Figure 1)VBG = VA (See Figure 1)

(Note13)

±1

Output+ & Output− connected to0.8V,

VBG = Floating, OutV = VA

1.2

0.33 xVA

0.23 xVA0.23 xVA

VVVVVpF

1, 2, 31, 2, 31, 2, 31, 2, 31, 2, 3

DIGITAL OUTPUT CHARACTERISTICS

LVDS Differential OutputVoltage

Change in LVDS OutputSwing Between LogicLevels

Output Offset VoltageOutput Offset VoltageOutput Offset VoltageChange Between LogicLevels

Output Short CircuitCurrent

Measured differentially,OutV = VA, VBG = FloatingMeasured differentially,

OutV = GND, VBG = Floating

780590

±4

mAmV

mVmVmV

580 380

920 720

mVP-PmVP-PmVP-PmVP-P

1, 2, 31, 2, 31, 2, 31, 2, 3

VOD

ΔVO DIFFVOSVOSΔVOS

8001100

IOS

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ADC08D1520QMLSymbolZOVOHVOL

Parameter

Differential OutputImpedance

CalRun H level outputCalRun L level output

ConditionsNotes (Note10)(Note10)

Typical(Note 7)1001.720.17

MinMax

UnitsΩVV

Sub-groups

IOH = −400 µAIOH = 400 µA

POWER SUPPLY CHARACTERISTICS

1:2 Demux OutputPD = PDQ = Low

PD = Low, PDQ = HighPD = PDQ = High1:2 Demux OutputPD = PDQ = Low

PD = Low, PDQ = HighPD = PDQ = High

Change in Full Scale Error withchange in

VA from 1.8V to 2.0V

248 MHz, 50 mVP-P injected onVA

8205651.5 2301250.018 21.32.9

875615 290170 2.21.49

mA (max)mA (max)mA mA (max)mA (max)mA W (max)W (max)mW

Analog Supply Current

1, 2, 31, 2, 3

IDR

Output Driver SupplyCurrent1, 2, 31, 2, 3

Power Consumption

1, 2, 31, 2, 3

PSRR1

D.C. Power SupplyRejection RatioA.C. Power SupplyRejection Ratio

PSRR251 dB

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ADC08D1520QMLAC Parameters

Symbol

Parameter

(Note 14)

Conditions

Notes

Typical(Note 7)2.010−18±0.5±1.07.47.246.345.44745−53.4−53−60−55−62−5855.553−50 1.77.04444−55−60−6550

44.1 6.1.1.5 47.5 7 43.9 43.9

2550 −45.2

Min

Max

Units

Sub-groups

−47.5

GHzError/SampledBFSdBFSBits (min)Bits (min)dB (min)dB (min)dB (min)dB (min)dB (max)dB (max)dBdBdBdBdB (min)dB (min)dB GHzBitsdBdBdBdBdBdB

4, 5, , 5, , 5, , 5, , 5, , 5, , 5, , 5, 6 4, 5, , 5, 6 4, 5, , 5, 6 4, 5, , 5, , 5, , 5, 6 4, 5, 6

Non-DES MODE DYNAMIC CONVERTER CHARACTERISTICS, 1:2 DEMUX MODEFPBWC.E.R. ENOBSINADSNRTHD2nd Harm

Full Power BandwidthCode Error RateGain Flatness

Effective Number of BitsSignal-to-Noise PlusDistortion RatioSignal-to-Noise RatioTotal Harmonic DistortionSecond HarmonicDistortion

Non-DES Mode

d.c. to 498 MHzd.c. to 1 GHz

fIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN1 = 365 MHz, VIN = FSR − 7 dBfIN2 = 375 MHz, VIN = FSR − 7 dB(VIN+) − (VIN−) > + Full Scale(VIN+) − (VIN−) < − Full ScaleDual Edge Sampling ModefIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dB

3rd HarmThird Harmonic DistortionSFDRIMD

Spurious-Free dynamicRange

Intermodulation DistortionOut of Range Output Code

INTERLEAVE MODE (DES Pin 127=VA/2) - DYNAMIC CONVERTER CHARACTERISTICS, 1:4 DEMUX MODEFPBWENOBSINADSNRTHD2nd Harm

Full Power BandwidthEffective Number of BitsSignal to Noise PlusDistortion RatioSignal to Noise RatioTotal Harmonic DistortionSecond HarmonicDistortion

Spurious Free DynamicRange

3rd HarmThird Harmonic DistortionSFDR

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ADC08D1520QMLAC Timing Parameters

Symbol

Parameter

AC TIMING CHARACTERISTICS

Maximum Input ClockFrequency

Minimum Input ClockFrequency

(Note 14)

Conditions

Notes

Typical(Note 7)

Min

Max

Units

Sub-groups

Non-DES Mode or DESMode in 1:2 Output DemuxNon-DES Mode or DESMode in Non-demux OutputNon-DES ModeDES Mode

200 MHz ≤ fCLK ≤ 1.5 GHz(Non-DES Mode)500 MHz ≤ fCLK ≤ 1.5 GHz(DES Mode)

(Note10)(Note10)(Note10)(Note10)

1.7 2005005050333333509030tOD + tOSK

150150

±50

ps (max)

1.51.0 55

GHzGHzMHzMHz% (min)% (max)% (min)% (max)ps (min)ps (min)%%psps CLK±Cyclespsps

9, 10, 119, 10, 11

9, 10, 11

fCLK(max)

fCLK(min)

Input Clock Duty Cycle

tCLtCH tSRtHRtSDtPWRtLHTtHLT

Input Clock Low TimeInput Clock High TimeDCLK Duty CycleSetup Time DCLK_RST±Hold Time DCLK_RST±

Synchronizing Edge to DCLK Output Delay

Pulse Width DCLK_RST±Differential Low-to-HighTransition TimeDifferential High-to-LowTransition Time

10% to 90%, CL = 2.5 pF10% to 90%, CL = 2.5 pF

tOSKtSUtHtADtAJtOD

DCLK-to-Data Output Skew

50% of DCLK transition to 50% of Data transition, SDRMode

and DDR Mode, 0° DCLKDDR Mode, 90° DCLKDDR Mode, 90° DCLKInput CLK+ Fall toAcquisition of Data

Data-to-DCLK Set-Up TimeDCLK-to-Data Hold TimeSampling (Aperture) DelayAperture Jitter

4005601.60.44

pspsnsps rmsns

Input Clock-to Data Output50% of Input Clock transition Delay (in addition to Pipelineto 50% of Data transitionDelay)

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ADC08D1520QMLSymbolParameterConditions

DI OutputsDId Outputs

Non-DESModeDESModeNon-DESModeDESMode

DI OutputsDId Outputs

Non-DESModeDESModeNon-DESModeDESMode

Notes

Typical(Note 7)13141313.5

MinMax

Units

Sub-groups

DQ Outputs

Pipeline Delay (Latency)1:2 Demux Mode

(Notes10, 12)

1414.513141313.5

(Notes10, 12)

1414.5

CLK±Cycles

DQd Outputs

DQ Outputs

Pipeline Delay (Latency)1:1 Demux Mode

DQd Outputs

Over Range Recovery Time

Differential VIN step from

±1.2V to 0V to get accurate conversion

15001152.511.51.033331.4 x 106

12801280

CLK±CyclensµsMHzns (min)ns (min)nsnsnsnsCLK±CyclesCLK±CyclesCLK±Cycles

9, 10, 119, 10, 11

tWUfSCLKtSSUtSHtHCStSCS tCALtCAL_LtCAL_H

PD low to Rated AccuracyNon-DES ModeConversion (Wake-Up Time)DES ModeSerial Clock FrequencyData to Serial Clock SetupTime

Data to Serial Clock HoldTime

CS to Serial Clock FallingEdge Hold Time

CS to Serial Clock RisingSetup Time

Serial Clock Low TimeSerial Clock High TimeCalibration Cycle TimeCAL Pin Low TimeCAL Pin High Time

See Figure 10See Figure 10

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ADC08D1520QMLPost Radiation Parameters DC Parameters

(Note 14)

Parameter

Conditions

DES/SCS up to 100 krad(Si)VIL

Logic Low Input Voltage

DES/SCS @ 300 krad(Si)Notes

Typical(Note 7)

Min

Max0.23 xVA0.15 xVA

UnitsVV

Sub-groups11

Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute MaximumRatings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specificationsand test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristicsmay degrade when the device is not operated under the listed test conditions.

Note 2:All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.

Note 3:When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA totwo. This limit is not placed upon the power, ground and digital output pins.

Note 4:Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor.

Note 5:The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.

30024704

Note 6:To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,achieving rated performance requires that the backside exposed pad be well grounded.

Note 7:Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to MIL-PRF-38535.

Note 8:Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, seeSpecification Definitions for Gain Error.

Note 9:The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin toground are isolated from the die capacitances by lead and bond wire inductances.

Note 10:This parameter is guaranteed by design and/or characterization and is not tested in production.

Note 11:The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the diecapacitances by lead and bond wire inductances.

Note 12:Each of the two converters of the ADC08D1520 has two LVDS output buses, which each clock data out at one half the sample rate. The data at eachbus is clocked out at one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one Input Clock cycle less than the latency of thefirst bus (Dd0 through Dd7). 1:2 Demux Mode.

Note 13:Tying VBG to the supply rail will increase the output offset voltage (VOS) by 300mv (typical), as shown in the VOS specification above. Tying VBG to thesupply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 30mV (typical).

Note 14:Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table.Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in MIL-STD-883, Method 1019Note 15:Refer to the Post Radiation Parameter Table

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ADC08D1520QMLSpecification Definitions

APERTURE (SAMPLING) DELAYis the amount of delay,measured from the sampling edge of the Clock input, afterwhich the signal present at the input pin is sampled inside thedevice.

APERTURE JITTER (tAJ) is the variation in aperture delayfrom sample to sample. Aperture jitter shows up as inputnoise.

CODE ERROR RATE (C.E.R.) is the probability of error andis defined as the probable number of word errors on the ADCoutput per unit of time divided by the number of words seenin that amount of time.. A C.E.R. of 10-18 corresponds to astatistical error in one word about every four (4) years.

CLOCK DUTY CYCLE is the ratio of the time that the clockwaveform is at a logic high to the total time of one clock period.DIFFERENTIAL NON-LINEARITY (DNL) is the measure ofthe maximum deviation from the ideal step size of 1 LSB.Measured at sample rate = 500 MSPS with a 1MHz inputsinewave.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVEBITS) is another method of specifying Signal-to-Noise andDistortion Ratio, or SINAD. ENOB is defined as (SINAD −1.76) / 6.02 and says that the converter is equivalent to a per-fect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH (FPBW) is a measure of thefrequency at which the reconstructed output fundamentaldrops 3 dB below its low frequency value for a full-scale input.GAIN ERROR is the deviation from the ideal slope of thetransfer function. It can be calculated from Offset and Full-Scale Errors:

Positive Gain Error = Offset Error − Positive Full-ScaleError

Negative Gain Error = −(Offset Error − Negative Full-Scale Error)

Gain Error = Negative Full-Scale Error − Positive Full-Scale Error = Positive Gain Error + Negative Gain Error

INTEGRAL NON-LINEARITY (INL) is a measure of worstcase deviation of the ADC transfer function from an idealstraight line drawn through the ADC transfer function. Thedeviation of any given code from this straight line is measuredfrom the center of that code value. The best fit method is used.INTERMODULATION DISTORTION (IMD) is the creation ofadditional spectral components as a result of two sinusoidalfrequencies being applied to the ADC input at the same time.It is defined as the ratio of the power in the second and thirdorder intermodulation products to the power in one of theoriginal frequencies. IMD is usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-est value or weight of all bits. This value is

VFS / 2N

where VFS is the differential full-scale amplitude VIN as set bythe FSR input and \"N\" is the ADC resolution in bits, which is8, for the ADC08D1520.

LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS)DIFFERENTIAL OUTPUT VOLTAGE (VOD) is the absolutevalue of the difference between the VD+ and VD- outputs; eachmeasured with respect to Ground.

30024746

FIGURE 1.

LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpointbetween the D+ and D- pins output voltage with respect toground; ie., [(VD+) +( VD-)]/2.

MISSING CODES are those output codes that are skippedand will never appear at the ADC outputs. These codes can-not be reached with any input value.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largestvalue or weight. Its value is one half of full scale.

NEGATIVE FULL-SCALE ERROR (NFSE) is a measure ofhow far the first code transition is from the ideal 1/2 LSB abovea differential −VIN/2 with the FSR pin low. For the AD-C08D1520 the reference voltage is assumed to be ideal, sothis error is a combination of full-scale error and referencevoltage error.

OFFSET ERROR (VOFF) is a measure of how far the mid-scale point is from the ideal zero voltage differential input.Offset Error = Actual Input causing average of 8k samples toresult in an average code of 127.5.

OUTPUT DELAY (tOD) is the time delay (in addition toPipeline Delay) after the falling edge of CLK+ before the dataupdate is present at the output pins.

OVER-RANGE RECOVERY TIME is the time required afterthe differential input voltages goes from ±1.2V to 0V for theconverter to recover and make a conversion with its rated ac-curacy.

PIPELINE DELAY (LATENCY) is the number of input clockcycles between initiation of conversion and when that data ispresented to the output driver stage. New data is available atevery clock cycle, but the data lags the conversion by thePipeline Delay plus the tOD.

POSITIVE FULL-SCALE ERROR (PFSE) is a measure ofhow far the last code transition is from the ideal 1-1/2 LSBbelow a differential +VIN/2. For the ADC08D1520 the refer-ence voltage is assumed to be ideal, so this error is a combi-nation of full-scale error and reference voltage error.

POWER SUPPLY REJECTION RATIO (PSRR) can be oneof two specifications. PSRR1 (DC PSRR) is the ratio of thechange in full-scale error that results from a power supplyvoltage change from 1.8V to 2.0V. PSRR2 (AC PSRR) is ameasure of how well an a.c. signal riding upon the powersupply is rejected from the output and is measured with a 248MHz, 50 mVP-P signal riding upon the power supply. It is theratio of the output amplitude of that signal at the output to itsamplitude on the power supply pin. PSRR is expressed in dB.SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed indB, of the rms value of the input signal at the output to the rmsvalue of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c.SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) orSINAD) is the ratio, expressed in dB, of the rms value of theinput signal at the output to the rms value of all of the other

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ADC08D1520QMLspectral components below half the input clock frequency, in-cluding harmonics but excluding d.c.

SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the differ-ence, expressed in dB, between the rms values of the inputsignal at the output and the peak spurious signal, where aspurious signal is any signal present in the output spectrumthat is not present at the input, excluding d.c.

TOTAL HARMONIC DISTORTION (THD) is the ratio ex-pressed in dB, of the rms total of the first nine harmonic levelsat the output to the level of the fundamental at the output. THDis calculated aswhere Af1 is the RMS power of the fundamental (output) fre-quency and Af2 through Af10 are the RMS power of the first 9harmonic frequencies in the output spectrum.

– Second Harmonic Distortion (2nd Harm) is the differ-ence, expressed in dB, between the RMS power in the inputfrequency seen at the output and the power in its 2nd har-monic level at the output.

– Third Harmonic Distortion (3rd Harm) is the differenceexpressed in dB between the RMS power in the input fre-quency seen at the output and the power in its 3rd harmoniclevel at the output.

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ADC08D1520QMLTransfer Characteristic

30024722

FIGURE 2. Input / Output Transfer Characteristic

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ADC08D1520QMLTiming Diagrams

30024714

FIGURE 3. SDR Clocking in 1:2 Demultiplexed Mode

30024759

FIGURE 4. DDR Clocking in 1:2 Demultiplexed and Non-DES Mode

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ADC08D1520QML30024760

FIGURE 5. DDR Clocking in Non-Demultiplexed and Non-DES Mode

30024719

FIGURE 6. Serial Interface Timing

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ADC08D1520QML30024720

FIGURE 7. Clock Reset Timing in DDR Mode

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FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE Low

30024724

FIGURE 9. Clock Reset Timing in SDR Mode with OUTEDGE High

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ADC08D1520QML30024725

FIGURE 10. On-Command Calibration Timing

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ADC08D1520QMLTypical Performance Characteristics

Non-DES Mode unless otherwise stated.

INL vs CODE

VA = VDR = 1.9V, fCLK = 1500 MHz, TA= 25°C, 1:2 Demux mode,

INL vs TEMPERATURE

30024730024765

DNL vs. CODEDNL vs. TEMPERATURE

3002476630024767

POWER DISSIPATION vs. SAMPLE RATEENOB vs. TEMPERATURE

3002478130024776

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ADC08D1520QMLENOB vs. SUPPLY VOLTAGEENOB vs. SAMPLE RATE

3002477730024778

ENOB vs. INPUT FREQUENCYSNR vs. TEMPERATURE

3002477930024768

SNR vs. SUPPLY VOLTAGESNR vs. SAMPLE RATE

3002476930024770

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ADC08D1520QMLSNR vs. INPUT FREQUENCYTHD vs. TEMPERATURE

3002477130024772

THD vs. SUPPLY VOLTAGETHD vs. SAMPLE RATE

3002477330024774

THD vs. INPUT FREQUENCYSFDR vs. TEMPERATURE

3002477530024785

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ADC08D1520QMLSFDR vs. SUPPLY VOLTAGESFDR vs. SAMPLE RATE

3002478430024782

SFDR vs. INPUT FREQUENCYSpectral Response at FIN = 373 MHz

3002478330024787

Spectral Response at FIN = 745 MHzCROSSTALK vs SOURCE FREQUENCY

3002478830024763

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ADC08D1520QMLFULL POWER BANDWIDTH

30024786

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ADC08D1520QML1.0 Functional Description

The ADC08D1520 is a versatile A/D Converter with an inno-vative architecture permitting very high speed operation. Thecontrols available ease the application of the device to circuitsolutions. Optimum performance requires adherence to theprovisions discussed here and in the Applications InformationSection.

While it is not recommended in radiation environments to al-low an active pin to float, pins 4, 14, 52 and 127 of theADC08D1520 are designed to be left floating without jeopardyin non radiation environments. In all discussions throughoutthis data sheet, whenever a function is called by allowing acontrol pin to float, connecting that pin to a potential of onehalf the VA supply voltage is recommended for radiation en-vironments.

1.1 OVERVIEW

The ADC08D1520 uses a calibrated folding and interpolatingarchitecture that achieves over 7.25 effective bits. The use offolding amplifiers greatly reduces the number of comparatorsand power consumption. Interpolation reduces the number offront-end amplifiers required, minimizing the load on the inputsignal and further reducing power requirements. In additionto other things, on-chip calibration reduces the INL bow oftenseen with folding architectures. The result is an extremelyfast, high performance, low power converter.

The analog input signal that is within the converter's inputvoltage range is digitized to eight bits at speeds of 200 MSPSto 1.7 GSPS, typical. Differential input voltages below nega-tive full-scale will cause the output word to consist of allzeroes. Differential input voltages above positive full-scalewill cause the output word to consist of all ones. Either ofthese conditions at either the I- or Q- Channel input will causethe OR (Out of Range) output to be activated. This single ORoutput indicates when the output code from one or both of thechannels is below negative full scale or above positive fullscale.

The output levels may be selected to be normal or reduced.Using reduced levels saves power but could result in erro-neous data capture of some or all of the bits, especially athigher sample rates and in marginally designed systems.1.1.1 Calibration

The ADC08D1520 has a calibration feature which must beinvoked by the user. If the device is powered-up in the Ex-tended Control Mode, the registers will be in an unknown stateand no calibration is performed. For the initial calibration afterpower-up, we recommend that the registers first be pro-grammed to a known state before performing a calibration orthe part be calibrated in the pin control mode. All subsequentcalibrations can be run in either the Non-Extended ControlMode or the Extended Control Mode.

The calibration algorithm consists of two portions. The firstportion is calibrating the analog input. This calibration trimsthe 100 Ω analog input differential termination resistor andminimizes full-scale error, offset error, DNL and INL, resultingin maximizing SNR, THD, SINAD (SNDR) and ENOB. Thisportion of the calibration can be disabled by programming theResistor Trim Disable (RTD) bit in the Extended Configuration

register in the Extended Control Mode. Disabling the inputtermination resistor is not recommended for the initial cali-bration after power-up. The second portion of the calibrationcycle is the ADC calibration in which internal bias currents areset. The ADC calibration is performed regardless of the RTDbit setting. Running the calibration is an important part of thischip’s functionality and is required in order to obtain specifiedperformance. In addition to the requirement that a calibrationbe run at power-up, a calibration must be run whenever theFSR pin is changed. For best performance, we recommendthat a calibration be run after application of power once thepower supplies have settled and the part temperature hasstabilized. Further calibrations should be run whenever theoperating temperature changes significantly relative to thespecific system performance requirements. See 2.5.2.1 Initi-ating Calibration for more information. Calibration can not beinitiated or run while the device is in the Power-Down Mode.See1.1.7 Power Down for information on the interaction be-tween Power down and calibration.

In normal operation, calibration should be performed just afterapplication of power and whenever a valid calibration com-mand is given. A calibration command can be issued usingtwo methods. The first method is to hold the CAL pin low forat least tCAL_L input clock cycles, then hold it high for at leastanother tCAL_H input clock cycles as defined in the ConverterElectrical Characteristics. The second method is to programthe CAL bit in the Calibration register. The functionality of theCAL bit is exactly the same as using the CAL pin. The CALbit must be programmed to 0b for tCAL_L input clock cycles andthen programmed to 1b for at least tCAL_H input clock cyclesto initiate a calibration cycle. The time taken by the calibrationprocedure is specified as tCAL in the Converter ElectricalCharacteristics.

The CAL bit does not reset itself to zero automatically, butmust be manually reset before another calibration event isdesired, the CAL bit may be left high indefinitely, with no neg-ative consequences.

The RTD bit setting is critical for running a calibration eventwith the Clock Phase Adjust enabled. If initiating a calibrationevent while the Clock Phase Adjust is enabled, the RTD bitmust be set to high, or no calibration will occur. If initiating acalibration event while the Clock Phase Adjust is not enabled,a normal calibration will occur, regardless of the setting of theRTD bit.

Calibration Operation Notes:

•During the calibration cycle, the OR output may be activeas a result of the calibration algorithm. All data on theoutput pins and the OR output are invalid during thecalibration cycle.

•During the calibration, all clocks are halted on chip,including internal clocks and DCLK, while the input

termination resistor is trimmed to a value that is equal toREXT / 33. This is to reduce noise during the input resistorcalibration portion of the calibration cycle. See forinformation on maintaining DCLK operation during on-command calibration.

This external resistor is located between pin 32 and

ground. REXT must be 3300 Ω ±0.1%. With this value, theinput termination resistor is trimmed to be 100 Ω. BecauseREXT is also used to set the proper current for the Trackand Hold amplifier, for the preamplifiers and for thecomparators, other values of REXT should not be used.•The CalRun output is high whenever the calibration

procedure is running. This is true whether the calibrationis done at power-up or on-command.

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ADC08D1520QML•

•

It is important that no digital activity take place on any ofthe digital input lines during the calibration process, exceptthat there must be a stable, constant frequency CLK signalpresent and that SCLK may be active if the EnhancedMode is selected. Actions that are not allowed include butare not limited to:Changing OUTV

Changing OutEdge or SDATA senseChanging between SDR and DDRChanging FSE or ECEChanging DCLK_RSTChanging SCSRaising PD highRaising CAL high

Doing any of these actions can cause faulty calibration.

1.1.2 Acquiring the Input

Data is acquired at the falling edge of CLK+ (pin 18) and thedigital equivalent of that data is available at the digital outputs13 input clock cycles later for the DI and DQ output buses and14 input clock cycles later for the DId and DQd output buses.There is an additional internal delay called tOD before the datais available at the outputs. See the Timing Diagram. The AD-C08D1520 will convert as long as the input clock signal ispresent. The fully differential comparator design and the in-novative design of the sample-and-hold amplifier, togetherwith self calibration, enables a very flat SINAD/ENOB re-sponse beyond 1.5 GHz. The ADC08D1520 output data sig-naling is LVDS and the output format is offset binary.1.1.3 Control Modes

Much of the user control can be accomplished with severalcontrol pins that are provided. Examples include initiation ofthe calibration cycle, Power Down Mode and full scale rangesetting. However, the ADC08D1520 also provides an Extend-ed Control mode whereby a serial interface is used to accessregister-based control of several advanced features. The Ex-tended Control mode is not intended to be enabled anddisabled dynamically. Rather, the user is expected to employeither the Non-Extended Control Mode or the Extended Con-trol Mode at all times. When the device is in the ExtendedControl Mode, pin-based control of several features is re-placed with register-based control and those pin-based con-trols are disabled. These pins are OutV (pin 3), OutEdge/DDR(pin 4), FSR (pin 14) and DES (pin 127). See 1.2 NON-EX-TENDED CONTROL/EXTENDED CONTROL for details onthe Extended Control Mode.

1.1.4 The Analog Inputs

The ADC08D1520 must be driven with a differential input sig-nal. Operation with a single-ended signal is not recommend-ed. It is important that the input signals are a.c. coupled to theinputs.

Two full-scale range settings are provided with pin 14 (FSR).A high on pin 14 causes an input full-scale range setting of ahigher VIN input level, while grounding pin 14 causes an inputfull-scale range setting of a reduced VIN input level. The full-scale range setting operates equally on both ADCs.

In the Extended Control Mode, the Input Full-Scale VoltageAdjust register allows the input full-scale range to be adjustedas described in 1.4 REGISTER DESCRIPTION and 2.3 THEANALOG INPUT.

1.1.5 Clocking

The ADC08D1520 must be driven with an a.c. coupled, dif-ferential clock signal. 2.4 THE CLOCK INPUTS describes theuse of the clock input pins. A differential LVDS output clock isavailable for use in latching the ADC output data into whateverdevice is used to receive the data.

The ADC08D1520 offers input and output clocking options.These options include a choice of Dual Edge Sampling (DES)or \"interleaved mode\" where the ADC08D1520 performs as asingle device converting at twice the input clock rate, a choiceof which DCLK edge the output data transitions on, and achoice of Single Data Rate (SDR) or Double Data Rate (DDR)outputs.

The ADC08D1520 also has the option to use a duty cyclecorrected clock receiver as part of the input clock circuit. Thisfeature is enabled by default and provides improved ADCclocking especially in the Dual-Edge Sampling Mode(DES). This circuitry allows the ADC to be clocked with asignal source having a duty cycle ratio of 20%/80% (worstcase) for both the Non-DES and the Dual Edge SamplingModes.

1.1.5.1 Dual-Edge Sampling

The DES Mode allows one of the ADC08D1520's inputs (I- orQ- Channel) to be sampled by both ADCs. One ADC samplesthe input on the positive edge of the input clock and the otherADC samples the same input on the other edge of the inputclock. A single input is thus sampled twice per input clock cy-cle, resulting in an overall sample rate of twice the input clockfrequency, or 3 GSPS with a 1.5 GHz input clock.

In this mode, the outputs must be carefully interleaved to re-construct the sampled signal. If the device is programmed intothe 1:2 Demultiplex Mode while in DES Mode, the data is ef-fectively Demultiplexed 1:4. If the input clock is 1.5 GHz, theeffective sampling rate is doubled to 3 GSPS and each of the4 output buses have a 750 MHz output rate. All data is avail-able in parallel. To properly reconstruct the sampled wave-form, the four bytes of parallel data that are output with eachclock are in the following sampling order from the earliest tothe latest and must be interleaved as such: DQd, DId, DQ, DI.Table 1 indicates what the outputs represent for the varioussampling possibilities. If the device is programmed into theNon-Demultiplex Mode, two bytes of parallel data are outputwith each edge of the clock in the following sampling order,from the earliest to the latest: DQ, DI. See Table 2.

In the Non-Extended Control Mode of operation only the I-channel input can be sampled in the DES Mode. In theExtended Control Mode of operation, the user can selectwhich input is sampled.

The ADC08D1520 also includes an automatic clock phasebackground calibration feature which can be used in DESMode to automatically and continuously adjust the clockphase of the I- and Q- channel. This feature removes the needto adjust the clock phase setting manually and provides opti-mal Dual-Edge Sampling ENOB performance.

IMPORTANT NOTE: The background calibration feature inDES Mode does not replace the requirement for calibration ifa large swing in ambient temperature is experienced by thedevice.

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ADC08D1520QMLTABLE 1. Input Channel Samples Produced at Data Outputs in 1:2 Demultiplexed Mode**

Data Outputs(Always sourced withrespect to fall of DCLK+)

Dual-Edge Sampling Mode (DES)

Non DES Sampling Mode

I- Channel Selected

Q- Channel Selected *Q- Channel Input Sampled withFall of CLK 13 cycles earlier.Q- Channel Input Sampled withFall of CLK 14 cycles earlier.

I- Channel Input Sampled

I- Channel Input Sampled with

with Fall of CLK 13 cycles

Fall of CLK 13 cycles earlier.

earlier.I- Channel Input Sampled

I- Channel Input Sampled with

with Fall of CLK 14 cycles

Fall of CLK 14 cycles earlier.

earlier.

DId

I- Channel Input Sampled

Q- Channel Input Sampled withQ- Channel Input Sampled with

with Rise of CLK 13.5 cycles

Fall of CLK 13 cycles earlier.Rise of CLK 13.5 cycles earlier.

earlier.I- Channel Input Sampled

Q- Channel Input Sampled withQ- Channel Input Sampled with

with Rise of CLK 14.5 cycles

Fall of CLK 14 cycles earlier.Rise of CLK 14.5 cycles earlier.

earlier.

DQd

* Note that, in DES + Non-DES Mode, only the I- Channel is sampled. In DES + Extended Control Mode, I- Channel or Q-Channel can be sampled.

** Note that, in the Non-Demultiplexed Mode, the DId and DQd outputs are disabled and are high impedance.

TABLE 2. Input Channel Samples Produced at Data Outputs in 1:1 Demultiplexed Mode

Data Outputs

(Sourced with respect to fall of DCLK+)

DIDldDQDQd

Non-DES Mode

DES Mode

I- Channel Input Sampled with Fall of CLKI- Channel Input Sampled with Fall of CLK13 cycles earlier.13 cycles earlier.No output.

Q- Channel Input Sampled with Fall ofCLK 13 cycles earlier.No output.

No output.

Q- Channel Input Sampled with Fall ofCLK 13.5 cycles earlier.No output.

the data rate and data is sent to the outputs on both edges ofDCLK. DDR clocking is enabled in Non-Extended ControlMode by tying pin 4 to VA/2.

1.1.5.4 Clocking Summary

The chip may be in one of four modes, depending on the Dual-Edge Sampling (DES) selection and the demultiplex selec-tion. For the DES selection, there are two possibilities: Non-DES Mode and DES Mode. In Non-DES Mode, each of thechannels (I-channel and Q-channel) functions independently,i.e. the chip is a dual 1.5 GSPS A/D converter. In DES Mode,the I- and Q-channels are interleaved and function togetheras one 3.0 GSPS A/D converter. For the demultiplex selec-tion, there are also two possibilities: Demux Mode and Non-Demux Mode. The I-channel has two 8-bit output bussesassociated with it: DI and DId. The Q-channel also has two 8-bit output busses associated with it: DQ and DQd. In DemuxMode, the channel is demultiplexed by 1:2. In Non-DemuxMode, the channel is not demultiplexed. Note that Non-De-mux Mode is also sometimes referred to as 1:1 Demux Mode.For example, if the I-channel was in Non-Demux Mode, thecorresponding digital output data would be available on onlythe DI bus. If the I-channel was in Demux Mode, the corre-sponding digital output data would be available on both theDI and DId busses, but at half the rate of Non-Demux Mode.Given that there are two DES Mode selections (DES Modeand Non-DES Mode) and two demultiplex selections (DemuxMode and Non-Demux Mode), this yields a total of four pos-

1.1.5.2 OutEdge and Demultiplex Control Setting

To help ease data capture in the SDR Mode, the output datamay be caused to transition on either the positive or the neg-ative edge of the output data clock (DCLK). In the Non-Extended Control Mode, this is chosen with the OutEdge input(pin 4). A high on the OutEdge input pin causes the outputdata to transition on the rising edge of DCLK+, while ground-ing this input causes the output to transition on the falling edgeof DCLK. See 2.5.3 Output Edge Synchronization. When inthe Extended Control Mode, the OutEdge is selected usingthe OED bit in the Configuration Register. This bit has twofunctions. In the single data rate (SDR) Mode, the bit functionsas OutEdge and selects the DCLK edge with which the datatransitions. In the Double Data Rate (DDR) Mode, this bit se-lects whether the device is in Non-Demultiplex or 1:2 Demul-tiplex Mode. In the DDR case, the DCLK has a 0° phaserelationship with the output data independent of the demulti-plexer selection.

For 1:2 Demux DDR 0 deg Mode, there are five, as opposedto four cycles of CLK delay from the deassertion ofDCLK_RST to the Synchronizing Edge. See 1.5 MULTIPLEADC SYNCHRONIZATION

1.1.5.3 Double Data Rate

A choice of single data rate (SDR) or double data rate (DDR)output is offered. With single data rate the output clock(DCLK) frequency is the same as the data rate of the two out-put buses. With double data rate the DCLK frequency is half

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ADC08D1520QMLsible modes: (1) Non-Demux Mode, (2) Non-Demux DESMode, (3) 1:2 Demux Non-DES Mode, and (4) 1:4 DemuxDES Mode. The following is a brief explanation of the termsand modes:

1.Non-Demux Mode: This mode is when the chip is in Non-Demux Mode and Non-DES Mode, but it is shortened tosimply \"Non-Demux Mode.\" The I- and Q- channelsfunction independently of one another. The digital outputdata is available for the I- channel on DI, and for the Q-channel on DQ.

2.Non-Demux DES Mode: This mode is when the chip is

in Non-Demux Mode and DES Mode. The I- and Q-channels are interleaved and function together as onechannel. The digital output data is available on the DI andDQ busses because although the chip is in Non-DemuxMode, both I- and Q- channels are functioning andpassing data.

3.1:2 Demux Non-DES Mode: This mode is when the chip

is in Demux Mode and Non-DES Mode. The I- and Q-channels function independently of one another. Thedigital output data is available for the I- channel on DI andDId, and for the Q- channel on DQ and DQd. This isbecause each channel (I- channel and Q- channel) isproviding digital data in a demultiplexed manner.

4.1:4 Demux DES Mode: This mode is when the chip is in

Demux Mode and DES Mode. The I- and Q- channelsare interleaved and function together as one channel.The digital output data is available on the DI, DId, DQ andDQd busses because although the chip is in DemuxMode, both I- and Q- channels are functioning andpassing data. To avoid confusion, this mode is labeled1:4 because the analog input signal is provided on onechannel and the digital output data is provided on fourbusses.

The choice of Dual Data Rate (DDR) and Single Data Rate(SDR) will only affect the speed of the output Data Clock(DCLK). Once the DES Modes and Demux Modes have beenchosen, the data output rate is also fixed. In the case of SDR,the DCLK runs at the same rate as the output data; outputdata may transition with either the rising or falling edge ofDCLK. In the case of DDR, the DCLK runs at half the rate ofthe output data; the output data transitions on both rising andfalling edges of the DCLK.

1.1.6 The LVDS Outputs

The data outputs, the Out Of Range (OR) and DCLK, areLVDS. Output current sources provide 3 mA of output currentto a differential 100 Ohm load when the OutV input (pin 14) ishigh or 2.2 mA when the OutV input is low. For short LVDSlines and low noise systems, satisfactory performance may

be realized with the OutV input low, which results in lowerpower consumption. If the LVDS lines are long and/or thesystem in which the ADC08D1520 is used is noisy, it may benecessary to tie the OutV pin high.

The LVDS data output have a typical common mode voltageof 800 mV when the VBG pin is left floating. This commonmode voltage can be increased to 1.1V by tying the VBG pinto VA if a higher common mode is required.

IMPORTANT NOTE: Tying the VBG pin to VA will also in-crease the differential LVDS output voltage by up to 40mV.1.1.7 Power Down

The ADC08D1520 is in the active state when the Power Downpin (PD) is low. When the PD pin is high, the device is in thePower Down Mode. In this Power Down Mode the data outputpins (positive and negative) are put into a high impedancestate and the devices power consumption is reduced to aminimal level. The DCLK+/- and OR +/- are not tri-stated, theyare weakly pulled down to ground internally. Therefore whenboth I- Channel and Q- Channel are powered down the DCLK+/- and OR +/- should not be terminated to a DC voltage.A high on the PDQ pin will power down the Q- Channel andleave the I- channel active. There is no provision to powerdown the I- Channel independently of the Q- Channel. Uponreturn to normal operation, the pipeline will contain meaning-less information.

If the PD input is brought high while a calibration is running,the device will not go into power down until the calibrationsequence is complete. However, if power is applied and PDis simultaneously ramped, the device will not calibrate untilthe PD input goes low. If a calibration is requested while thedevice is powered down, the calibration request will be com-pletely ignored. Calibration will function with the Q- Channelpowered down, but that channel will not be calibrated if PDQis high. If the Q- Channel is subsequently to be used, it isnecessary to perform a calibration after PDQ is brought low.1.2 NON-EXTENDED CONTROL/EXTENDED CONTROLThe ADC08D1520 may be operated in one of two modes. Inthe simpler Non-Extended Control Mode, the user affectsavailable configuration and control of the device through sev-eral control pins. The \"Extended Control Mode\" provides ad-ditional configuration and control options through a serialinterface and a set of 9 registers. Extended Control Mode isselected by setting pin 41 to logic low. The choice of controlmodes is required to be a fixed selection and is not intendedto be switched dynamically while the device is operational.Table 3 shows how several of the device features are affectedby the control mode chosen.

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ADC08D1520QMLTABLE 3. Features and Modes

Feature

Non-Extended Control Mode

Extended Control Mode

Selected with bit 10 nDE in the Configuration Register(Addr-1h; bit-10)

Selected with DCP in the ConfigurationRegister (Addr-1h; bit-11)

SDR or DDR ClockingSelected with pin 4DDR Clock PhaseSDR Data transitionswith rising or fallingDCLK edge

Not Selectable (0° Phase Only)

SDR Data transitions with rising

edge of DCLK+ when pin 4 is highSelected with OED in the Configuration Register (Addr-1h; bit-8)and on falling edge when low.

Normal differential data and DCLKamplitude selected when pin 3 is

Selected with OV in the Configuration Register (Addr-1h; bit-9)

high and reduced amplitudeselected when low.

Normal input full-scale rangeselected when pin 14 is high andreduced range when low.

Selected range applies to bothchannels.Not possible

Up to 512 step adjustments over a nominal range specified in 1.4REGISTER DESCRIPTION. Separate range selected for I-Channel and Q- Channels. Selected using Full RangeRegisters (Addr-3h and Bh; bit-7 thru 15)

512 steps of adjustment using the input Offset register specifiedin 1.4 REGISTER DESCRIPTION for each channel using InputOffset registers (Addr-2h and Ah; bit-7 thru 15)

Enabled by programming DEN in the Extended ConfigurationRegister (Addr-9h; bit-13 )

Either I- Channel or Q- Channel input may be sampled by bothADCs.

A test pattern can be made present at the data outputs by settingTPO to 1b in Extented Configuration Register (Addr-9h; bit-15)The DCLK outputs will continuously be present when RTD is setto 1b in Extented Configuration Register (Addr-9h; bit-14)If the device is set in DDR, the output can be programmed to benon-demultiplex. When OED in Configuration Register is set 1b(Addr-1h; 8-bit), this selects non-demultiplex. If OED is set 0b,this selects 1:2 demultiplex.

The OR outputs can be programmed to become a second DCLKoutput when nSD is set 0b in Configuration Register(Addr-1h; bit-13).

The sampling clock phase can be manually adjusted through theCoarse and Intermediate Register (Addr-Fh; bit-14 to 7) and Fineregister (Addr-Dh; bit-15 to 8)

in the Non-Extended Control Mode and the user switches tothe Extended Control Mode after the part has stabilized, theregisters will load with the register default states described inTable 4.

LVDS output level

Full-Scale Range

Input Offset AdjustDual Edge SamplingSelection

Dual Edge SamplingInput ChannelSelectionTest Pattern

Enabled with pin 127 set to VA/2Only I-Channel Input can be used

Not possible

Resistor Trim DisableNot possible

Selectable OutputDemultiplexer

Not possible

Second DCLK OutputNot possible

Sampling Clock Phase

Not possible

Adjust

IMPORTANT NOTE: When the device is powered up in theExtended Control Mode, the Registers are loaded with invaliddata and the Registers come up in an unknown state. Beforeinitiating a calibration the registers must be written to andprogrammed into a known state. If the device is powered up

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ADC08D1520QMLTABLE 4. Extended Control Mode Operation

(Pin 41 Logic Low)

Feature

SDR or DDR ClockingDDR Clock PhaseLVDS Output AmplitudeFull-Scale RangeInput Offset AdjustDual Edge Sampling (DES)

Test PatternResistor Trim DisableSelectable Output Demultiplexer

Second DCLK OutputSampling Clock Phase Adjust

1.3 THE SERIAL INTERFACE

The 3-pin serial interface is enabled only when the device isin the Extended Control mode. The pins of this interface areSerial Clock (SCLK), Serial Data (SDATA) and Serial Inter-face Chip Select (SCS). Nine write only registers are acces-sible through this serial interface.

SCS: This signal should be asserted low while accessing aregister through the serial interface. Setup and hold times withrespect to the SCLK must be observed.

SCLK: Serial data input is accepted at the rising edge of thissignal.

SDATA: Each register access requires a specific 32-bit pat-tern at this input. This pattern consists of a header, registeraddress and register value. The data is shifted in MSB first.Setup and hold times with respect to the SCLK must be ob-served. See the Timing Diagram.

Each Register access consists of 32 bits, as shown in Figure6 of the Timing Diagrams. The fixed header pattern is 00000000 0001 (eleven zeros followed by a 1). The loading se-quence is such that a \"0\" is loaded first. These 12 bits formthe header. The next 4 bits are the address of the register thatis to be written to and the last 16 bits are the data written tothe addressed register. The addresses of the various regis-ters are indicated in Table 5.

Refer to the Register Description (1.4 REGISTER DESCRIP-TION) for information on the data to be written to the registers.Subsequent register accesses may be performed immediate-ly, starting with the 33rd SCLK. This means that the SCS inputdoes not have to be de-asserted and asserted again betweenregister addresses. It is possible, although not recommended,to keep the SCS input permanently enabled (at a logic low)when using extended control.

IMPORTANT NOTE: Do not write to the Serial Interface whencalibrating the ADC. Doing so will impair the performance ofthe device until it is re-calibrated correctly. Programming theserial registers will also reduce dynamic performance of theADC for the duration of the register access time.

Extended Control Mode Default State

DDR Clocking

Data changes with DCLK edge (0° phase)

Normal amplitude

(VOD)

700 mV nominal for both channelsNo adjustment for either channel

Not enabledNot present at output

Trim enabled, DCLK not continuously present at output

1:2 demultiplex

Not present, pin 79 and 80 function as OR+ and OR-.

No adjustment for fine, intermediate or coarse

TABLE 5. Register Addresses

4-Bit Address

Loading Sequence:

A3 loaded after H0, A0 loaded last

A3000000001111111

A2000011110000111

A1001100110011001

A0010101010101010

Hex0h1h2h3h4h5h6h7h8h9hAhBhChDhEh

CalibrationConfigurationI- Ch OffsetI- Ch Full-ScaleVoltage AdjustReservedReservedReservedReservedReservedExtendedConfigurationQ- Ch OffsetQ- Ch Full-ScaleVoltage Adjust

ReservedReservedSampling Clock Phase

Fine AdjustSample Clock PhaseIntermediate andCoarse Adjust

1111Fh

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ADC08D1520QML1.4 REGISTER DESCRIPTION

Nine write-only registers provide several control and config-uration options in the Extended Control Mode. These regis-ters have no effect when the device is in the Non-ExtendedControl Mode. Each register description below also shows theRegister Default State.

Calibration Register

Addr: 0h (0000b)D15CALD71Bit 15

D141D61

D131D51

D121D41

D111D31

Write only (0x7FFF)D101D21

D91D11

D81D01

Bit 10

Bit 9

Bits 14:0

CAL: Calibration Enable. When this bit is set1b, a command calibration cycle is initiated.This function is exactly the same as issuinga calibration using the CAL pin. See section2.5.2.1, Initiating Calibration for details forusage.

Default State: 0bMust be set to 1b

Configuration Register

Bit 8

Addr: 1h (0001b)D151D71Bit 15Bit 14Bit 13

D140D61

D13nSDD51

D12

D11

Write only (0xB2FF)D10nDED21

D9OVD11

D8OEDD01

DCSDCPD41

D31

Bit 12

Bit 11

Must be set to 1bMust be set to 0b

nSD: Second DCLK Output. When this bit is1b, the device only has one DCLK output andone OR output. When this output is 0b, thedevice has two identical DCLK outputs and noOR output.

Default State: 1b

DCS: Duty Cycle Stabilizer. When this bit is setto 1b, a duty cycle stabilization circuit isapplied to the clock input. When this bit is setto 0b the stabilization circuit is disabled.Default State: 1b

DCP: DDR Clock Phase. This bit only has aneffect in the DDR Mode. When this bit is set to0b, the DCLK edges are time-aligned with thedata bus edges (\"0° Phase\"). When this bit isset to 1b, the DCLK edges are placed in themiddle of the data bit-cells (\"90° Phase\"),using the one-half speed DCLK shown inFigure 4 as the phase reference.Default State: 0b

Bits 7:0

nDE: DDR Enable. When this bit is set to 0b,data bus clocking follows the DDR (DoubleData Rate) Mode whereby a data word isoutput with each rising and falling edge ofDCLK. When this bit is set to a 1b, data busclocking follows the SDR (single data rate)Mode whereby each data word is output witheither the rising or falling edge of DCLK , asdetermined by the OutEdge bit.Default State: 0b

OV: Output Voltage. This bit determines theLVDS outputs' voltage amplitude and has thesame function as the OutV pin that is used inthe Non-Extended Control Mode. When this bitis set to 1b, the standard output amplitude of780 mVP-P is used. When this bit is set to 0b,the reduced output amplitude of 590 mVP-P isused.

Default State: 1b

OED: Output Edge and Demultiplex Control.This bit has two functions. When the device isin SDR Mode, this bit selects the DCLK edgewith which the data words transition in theSDR Mode and has the same effect as theOutEdge pin in the Non-Extended ControlMode. When this bit is set to 1b, the dataoutputs change with the rising edge of DCLK+. When this bit is set to 0b, the data outputchanges with the falling edge of DCLK+. Whenthe device is in DDR Mode, this bit selects theNon-Demultiplexed Mode when set to 1b.When the bit set to 0b, the device isprogrammed into the 1:2 Demultiplexed Mode.The 1:2 Demultiplexed Mode is the defaultmode. In DDR Mode, DCLK has a 0° phaserelationship with the data.Default State: 0bMust be set to 1b

IMPORTANT NOTE: It is recommended that this registershould only be written upon power-up initialization as writingit may cause disturbance on the DCLK output as this signalsbasic configuration is changed.

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ADC08D1520QMLI-Channel Offset

Addr: 2h (0010b)D15(MSB)D7SignBits 15:8

D61

D51

D14

D13

D12

D11

Write only (0x007F)D10

D8(LSB)

D21

D11

D01

Bit 15

Offset ValueD41

D31

TPO: Test Pattern Output. When this bit is set1b, the ADC is disengaged and a test patterngenerator is connected to the outputs

including OR. This test pattern will work withthe device in the SDR, DDR and the Non-Demultiplex output modes.Default State: 0b

RTD: Resistor Trim Disable. When this bit isset to 1b, the input termination resistor is nottrimmed during the calibration cycle and theDCLK output remains enabled. Note that theADC is calibrated regardless of this setting.Default State: 0b

DES: DES Enable. Setting this bit to 1benables the Dual Edge Sampling Mode. Inthis mode the ADCs in this device are usedto sample and convert the same analog inputin a time-interleaved manner, accomplishinga sample rate of twice the input clock rate.When this bit is set to 0b, the device operatesin the Non-DES Mode.Default State: 0b

IS: Input Select. When this bit is set to 0b theI- Channel input is operated upon by bothADCs. When this bit is set to 1b the Q-Channel input is operated on by both ADCs.Default State: 0bMust be set to 0b

DLF: DES Low Frequency. When this bit isset 1b, the dynamic performance of thedevice is improved when the input clock isless than 900 MHz.Default State: 0bMust be set to 1b

Q- Channel Offset

Bit 14

Bit 7

Bit 6:0

Offset Value. The input offset of the I-ChannelADC is adjusted linearly and monotonically bythe value in this field. 00h provides a nominalzero offset, while FFh provides a nominal 45mV of offset. Thus, each code step provides0.176 mV of offset.

Default State: 0000 0000 b

Sign bit. 0b gives positive offset, 1b givesnegative offset.Default State: 0bMust be set to 1b

I-Channel Full-Scale Voltage Adjust

Bit 13

Addr: 3h (0011b)D15(MSB)D7(LSB)Bit 15:7

D61

D51

D14

D13

D12

Write only (0x807F)D11

D10

Bit 12

Adjust ValueD41

D31

D21

D11

D01

Bit 11Bit 10

Full Scale Voltage Adjust Value. The input full-scale voltage or gain of the I-Channel ADC isadjusted linearly and monotonically with a 9 bitdata value. The adjustment range is ±20% ofthe nominal 700 mVP-P differential value.0000 0000 01000 0000 0Default Value1111 1111 1

560mVP-P700mVP-P840mVP-P

Bits 9:0

Addr: Ah (1010b)D15(MSB)D7SignBit 15:8

D61

D51

D14

D13

D12

D11

Write only (0x007F)D10

D8(LSB)

D21

D11

D01

Bits 6:0

For best performance, it is recommended thatthe value in this field be limited to the range of0110 0000 0b to 1110 0000 0b. i.e., limit theamount of adjustment to ±15%. The remaining±5% headroom allows for the ADC's own fullscale variation. A gain adjustment does notrequire ADC re-calibration.

Default State: 1000 0000 0b (no adjustment)Must be set to 1b

Extended Configuration Register

Offset ValueD41

D31

Addr: 9h (1001b)D15TPOD71

D14RTDD61

D13DEND51

D12ISD41

D110D31

Write only (0x03FF)D10DLFD21

D91D11

D81D01

Bit 6:0Bit 7

Offset Value. The input offset of the Q-Channel ADC is adjusted linearly and

monotonically by the value in this field. 00hprovides a nominal zero offset, while FFhprovides a nominal 45 mV of offset. Thus,each code step provides about 0.176 mV ofoffset.

Default State: 0000 0000 b

Sign bit. 0b gives positive offset, 1b givesnegative offset.Default State: 0bMust be set to 1b

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ADC08D1520QMLQ- Channel Full-Scale Voltage Adjust

Addr: Bh (1011b)D15(MSB)D7(LSB)Bit 15:7

D61

D51

D14

D13

D12

Write only (0x807F)D11

D10

Bit 15

Polarity Select. When this bit is selected, thepolarity of the ADC sampling clock isinverted.

Default State: 0b

Adjust ValueD41

D31

D21

D11

D01

Bits 14:10Coarse Phase Adjust. Each code value in

this field delays the sample clock by

approximately 65 ps. A value of 00000b inthis field causes zero adjustment.Default State: 00000bBits 9:7

Intermediate Phase Adjust. Each code valuein this field delays the sample clock by

approximately 11 ps. A value of 000b in thisfield causes zero adjustment. Maximumcombined adjustment using Coarse PhaseAdjust and Intermediate Phase adjust isapproximately 2.1ns.Default State: 000bMust be set to 1b

Full Scale Voltage Adjust Value. The input full-scale voltage or gain of the I- Channel ADC isadjusted linearly and monotonically with a 9 bitdata value. The adjustment range is ±20% ofthe nominal 700 mVP-P differential value.0000 0000 01000 0000 01111 1111 1

560 mVP-P700 mVP-P840 mVP-P

Bits 6:0

Default State: 1000 0000 0b (no adjustment)Must be set to 1b

Sample Clock Phase Fine Adjust

Addr: Eh (1110b)D15(MSB)D71Bits 15:8

D61D14

D13

D12

D11

Write only (0x00FF)D10

D8(LSB)D11

D01

Fine Phase AdjustD51

D41

D31

D21

Note Regarding Extended Mode Offset Correction

When using the I- Channel or Q- Channel Offset Adjust reg-isters, the following information should be noted.

For offset values of +0000 0000 and -0000 0000, the actualoffset is not the same. By changing only the sign bit in thiscase, an offset step in the digital output code of about 1/10thof an LSB is experienced. This is shown more clearly in theFigure below.

Note Regarding Clock Phase Adjust

This is a feature intended to help the system designer removesmall imbalances in clock distribution traces at the board levelwhen multiple ADCs are used. Please note, however, thatenabling this feature will reduce the dynamic performance(ENOB, SNR SFDR) some finite amount. The amount ofdegradation increases with the amount of adjustment applied.The user is strongly advised to (a) use the minimal amount ofadjustment: and (b) verify the net benefit of this feature in hissystem before relying on it.

Fine Phase Adjust. The phase of the ADCsampling clock is adjusted linearly and

monotonically by the value in this field. 00hprovides a nominal zero phase adjustment,while FFh provides a nominal 50 ps of delay.Thus, each code step provides about 0.2 psof delay.

Default State: 0000 0000bMust be set to 1b

Bits 7:0

Sample Clock Phase Intermediate/Coarse AdjustAddr: Fh (1111b)D15POLD7(LSB)

D14

D13

D12

Write only (0x007F)D11

D10

D9IPAD11

D01

FIGURE 11. Extended Mode Offset Behavior

30024730

(MSB) Coarse Phase AdjustD61

D51

D41

D31

D21

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ADC08D1520QML1.5 MULTIPLE ADC SYNCHRONIZATION

The ADC08D1520 has the capability to precisely reset itssampling clock input to DCLK output relationship as deter-mined by the user-supplied DCLK_RST pulse. This allowsmultiple ADCs in a system to have their DCLK (and data) out-puts transition at the same time with respect to the sharedCLK input that they all the ADCs use for sampling.

The DCLK_RST signal must observe some timing require-ments that are shown in Figure 7, Figure 8 and Figure 9 of theTiming Diagrams. The DCLK_RST pulse must be of a mini-mum width and its deassertion edge must observe setup andhold times with respect to the CLK input rising edge. Thesetiming specifications are listed as tRH, tRS, and tRPW in theConverter Electrical Characteristics.

The DCLK_RST signal can be asserted asynchronous to theinput clock. If DCLK_RST is asserted, the DCLK output is heldin a designated state. The state in which DCLK is held duringthe reset period is determined by the mode of operation (SDR/DDR) and the setting of the Output Edge configuration pin orbit. (Refer to Figure 7, Figure 8 and Figure 9 for the DCLKreset state conditions). Therefore, depending upon when theDCLK_RST signal is asserted, there may be a narrow pulseon the DCLK line during this reset event. When theDCLK_RST signal is de-asserted in synchronization with theCLK rising edge, the 4th or 5th CLK falling edge synchronizesthe DCLK output with those of other ADC08D1520's in thesystem. The DCLK output is enabled again after a constantdelay (relative to the input clock frequency) which is equal tothe CLK input to DCLK output delay (tSD). The device alwaysexhibits this delay characteristic in normal operation.

As shown in Figure 7, Figure 8 and Figure 9of the Timing Di-agrams, there is a delay from the deassertion of DCLK_RSTto the reappearance of DCLK, which is equal to several CLKcycles of delay plus tSD. Note that the deassertion ofDCLK_RST is not latched in until the next falling edge of CLK.For 1:2 Demux DDR 0 deg Mode, there are five CLK cyclesof delay; for all other modes, there are four CLK cycles ofdelay.

If the device is not programmed to allow DCLK to run contin-uously, DCLK will become inactive during a calibration cycle.Therefore, it is strongly recommended that DCLK only beused as a data capture clock and not as a system clock.The DCLK_RST pin should NOT be brought high while thecalibration process is running (while CalRun is high). Doingso could cause a digital glitch in the digital circuitry, resultingin corruption and invalidation of the calibration. (See Applica-tion Information Section 2.4.3)

1.6 ADC TEST PATTERN

To aid in system debug, the ADC08D1520 has the capabilityof providing a test pattern at the four output ports completelyindependent of the input signal. The ADC is disengaged anda test pattern generator is connected to the outputs includingOR. The test pattern output is the same in DES Mode andNon-DES Mode. Each port is given a unique 8-bit word, al-ternating between 1's and 0's as described in the Table 6.

TABLE 6. Test Pattern by Output Port

in 1:2 Demultiplex Mode

TimeT0T1T2T3T4T5T6T7T8T9T10T11

Qd01hFEh01hFEh01h01hFEh01hFEh01h01h...

Id02hFDh02hFDh02h02hFDh02hFDh02h02h...

Q03hFCh03hFCh03h03hFCh03hFCh03h03h...

I04hFBh04hFBh04h04hFBh04hFBh04h04h...

OR01010010100...

PatternSequence n+2PatternSequencen+1PatternSequence

nComments

With the part programmed into the Non-Demultiplex Mode,the test pattern’s order will be as described in Table 7.

TABLE 7. Test Pattern by Output Port in

Non-Demultiplex ModeTimeT0T1T2T3T4T5T6T7T8T9T10T11T12T13T14T15

Q01hFEh01h01hFEhFEh01h01hFEh01h01hFEh01h01hFEh...

I02hFDh02h02hFDhFDh02h02hFDh02h02hFDh02h02hFDh...

OR010011001001001...

PatternSequencen+1PatternSequence

nComments

To ensure that the test pattern starts synchronously in eachport, set DCLK_RST while writing the Test Pattern Output bitin the Extended Configuration Register. The pattern appearsat the data output ports when DCLK_RST is cleared low. Thetest pattern will work at speed and will work with the device inthe SDR, DDR and the Non-Demultiplex output modes.

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ADC08D1520QML2.0 Applications Information

2.1 APPLICATIONS IN RADIATION ENVIRONMENTS

Applying the ADC08D1520 in a radiation environment shouldbe done with careful consideration to that environment. TheQMLV version of this part has been rated to tolerate a hightotal dose of ionizing radiation by test method 1019 of MIL-STD-883. The part is also immune to SEE (Single EventEffects) hard errors such as Single Event Latch-up and Func-tional Interrupts. However, there are still some recommenda-tions and cautions.

2.1.1 Total Ionizing Dose

Radiation hardness assured (RHA) products are those partnumbers with a total ionizing dose (TID) level specified in theOrdering Information table on the front page. Testing andqualification of these products is done on a wafer level ac-cording to MIL-STD-883, Test Method 1019. Wafer level TIDdata is available with lot shipments.

2.1.2 Single Event Effects

One time single event latch-up testing (SEL) was preformedaccording to EIA/JEDEC Standard, EIA/JEDEC57. The linearenergy transfer threshold (LETth) shown in the Key Specifi-cations table on the front page is the maximum LET tested.No evidence of Single Event Latch-up (SEL) or Single EventFunctional Interrupt was seen. A test report is available uponrequest.

2.1.3 Floating pins

There are four tri-level pins which activate the followingmodes when left floating: FSR/DCLK_RST-, OutEdge/DDR/SDATA, DRST_SEL and DES/SCS. If modes requiring afloating pin are needed to be used, then it is strongly recom-mended that the floating method of establishing Va/2 on thesepins not be employed. Due to the potential of increased leak-age of the input protection diodes after large ionizing doses,the midpoint voltage (Va/2 or 0.95V) should be voltage forcedor formed with a resistor divider from the analog supply toground with two 2K ohm resistors. The tolerance for this midpoint voltage is 650mV ≥ VA/2 ≤ 1.2V. The internal voltagedivider resistors provide too little current to set the midpointvoltage reliably in radiation environments.

2.2 THE REFERENCE VOLTAGE

The voltage reference for the ADC08D1520 is derived from a1.2V bandgap reference, a buffered version of which ismade available at pin 31, VBG, for user convenience. Thisoutput has an output current capability of ±100 μA and shouldbe buffered if more current is required.

The internal bandgap-derived reference voltage has a nomi-nal value VIN, as determined by the FSR pin and described in1.1.4 The Analog Inputs.

There is no provision for the use of an external reference volt-age, but the full-scale input voltage can be adjusted througha Full Scale Register in the Extended Control Mode, as ex-plained in 1.2 NON-EXTENDED CONTROL/EXTENDEDCONTROL.

Differential input signals up to the chosen full-scale level willbe digitized to 8 bits. Signal excursions beyond the full-scalerange will be clipped at the output. These large signal excur-sions will also activate the OR output for the time that thesignal is out of range. See 2.3.2 Out Of Range (OR) Indica-tion.

One extra feature of the VBG pin is that it can be used to raisethe common mode voltage level of the LVDS outputs. Theoutput offset voltage (VOS) is typically 800 mV when the VBGpin is used as an output or left unconnected. To raise theLVDS offset voltage to a typical value of 1100 mV the VBG pincan be connected directly to the supply rails.

2.3 THE ANALOG INPUT

The analog input is a differential one to which the signalsource must be a.c. coupled as shown in Figure 12. In theNon-Extended Control Mode, the full-scale input range is se-lected with the FSR pin as specified in the Converter ElectricalCharacteristics. In the Extended Control Mode, the full-scaleinput range is selected by programming the Full-Scale Volt-age Adjust register through the Serial Interface. For bestperformance, when adjusting the input full-scale range in theExtended Control, refer to 1.4 REGISTER DESCRIPTION forguidelines on limiting the amount of adjustment.

Table 8 gives the input to output relationship with the FSR pinhigh when the normal (Non-Extended) Mode is used. With theFSR pin grounded, the millivolt values in Table 8 are reducedto 75% of the values indicated. In the Extended Control Mode,these values will be determined by the full scale range andoffset settings in the Control Registers.

TABLE 8. Differential Input To Output Relationship

(Non-Extended Control Mode, FSR High)

VIN+VCM − 225 mVVCM − 113 mV

VCM

VCM + 109 mVVCM + 217.5 mV

VIN−VCM + 225 mVVCM + 113 mV

VCMVCM −109 mVVCM − 217.5 mV

Output Code0000 00000100 00000111 1111 /1000 00001100 00001111 1111

The buffered analog inputs simplify the task of driving theseinputs and the RC pole that is generally used at sampling ADCinputs is not required. If it is desired to use an amplifier circuitbefore the ADC, use care in choosing an amplifier with ade-quate noise and distortion performance and adequate gain atthe frequencies used for the application.

IMPORTANT NOTE: An Analog input channel that is not used(e.g. in DES Mode) should be left floating when the inputs area.c. coupled. Do not connect an unused analog input toground.

30024744

FIGURE 12. Differential Input Drive

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ADC08D1520QML2.3.1 Handling Single-Ended Input Signals

There is no provision for the ADC08D1520 to adequately pro-cess single-ended input signals. The best way to handlesingle-ended signals is to convert them to differential signalsbefore presenting them to the ADC. The easiest way to ac-complish single-ended to differential signal conversion is withan appropriate balun-connected transformer, as shown inFigure 13.

2.3.1.1. a.c. Coupled Input

The easiest way to accomplish single-ended a.c. Input to dif-ferential a.c. signal is with an appropriate balun, as shown inFigure 13.

2.3.3 Full-Scale Input Range

As with all A/D Converters, the input range is determined bythe value of the ADC's reference voltage. The reference volt-age of the ADC08D1520 is derived from an internal band-gapreference. The FSR pin controls the effective reference volt-age of the ADC08D1520 such that the differential full-scaleinput range at the analog inputs is a normal amplitude withthe FSR pin high, or a reduced amplitude with FSR pin low asdefined by the specification VIN in the Converter ElectricalCharacteristics. Best SNR is obtained with FSR high.2.4 THE CLOCK INPUTS

The ADC08D1520 has differential LVDS clock inputs, CLK+and CLK-, which must be driven with an a.c. coupled, differ-ential clock signal. Although the ADC08D1520 is tested andits performance is guaranteed with a differential 1.5 GHzclock, it typically will function well with input clock frequenciesindicated in the Converter Electrical Characteristics. Theclock inputs are internally terminated and biased. The inputclock signal must be capacitive coupled to the clock pins asindicated in Figure 14.

Operation up to the sample rates indicated in the ConverterElectrical Characteristics is typically possible if the maximumambient temperatures indicated are not exceeded. Operatingat higher sample rates than indicated for the given ambienttemperature may result in reduced device reliability and prod-uct lifetime. This is because of the higher power consumptionand die temperatures at high sample rates. Important also forreliability is proper thermal management. See 2.7.2 ThermalManagement.

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FIGURE 13. Single-Ended to Differential Signal

Conversion using a BalunFigure 13 is a generic depiction of a single-ended to differen-tial signal conversion using a balun. The circuitry specific tothe balun will depend upon the type of balun selected and theoverall board layout. It is recommended that the system de-signer contact the manufacturer of the balun they have se-lected to aid in designing the best performing single-ended todifferential conversion circuit using that particular balun.

When selecting a balun, it is important to understand the inputarchitecture of the ADC. There are specific balun parametersof which the system designer should be mindful. A designershould match the impedance of the analog source to theADC08D1520’s on-chip 100Ω differential input terminationresistor. The range of this input termination resistor is de-scribed in the Converter Electrical Characteristics as thespecification RIN.

Also, the phase and amplitude balance are important. Thelowest possible phase and amplitude imbalance is desiredwhen selecting a balun. The phase imbalance should be nomore than ±2.5° and the amplitude imbalance should be lim-ited to less than 1dB at the desired input frequency range.Finally, when selecting a balun, the VSWR (Voltage StandingWave Ratio), bandwidth and insertion loss of the balun shouldalso be considered. The VSWR aids in determining the overalltransmission line termination capability of the balun when in-terfacing to the ADC input. The insertion loss should beconsidered so that the signal at the balun output is within thespecified input range of the ADC as described in the Con-verter Electrical Characteristics as the specification VIN.2.3.2 Out Of Range (OR) Indication

When the conversion result is clipped the Out of Range outputis activated such that OR+ goes high and OR- goes low. Thisoutput is active as long as accurate data on either or both ofthe buses would be outside the range of 00h to FFh. Note thatwhen the device is programmed to provide a second DCLKoutput, the OR signals become DCLK2. Refer to 1.4 REGIS-TER DESCRIPTION.

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FIGURE 14. Differential (LVDS) Input Clock ConnectionThe differential input clock line pair should have a character-istic impedance of 100Ω and (when using a balun), be termi-nated at the clock source in that (100 Ω) characteristicimpedance. The input clock line should be as short and asdirect as possible. The ADC08D1520 clock input is internallyterminated with an untrimmed 100Ω resistor.

Insufficient input clock levels will result in poor dynamic per-formance. Excessively high input clock levels could cause achange in the analog input offset voltage. To avoid theseproblems, keep the input clock level within the range specifiedin the Converter Electrical Characteristics.

The low and high times of the input clock signal can affect theperformance of any A/D Converter. The ADC08D1520 fea-tures a duty cycle clock correction circuit which can maintainperformance over temperature even in DES Mode. The ADCwill meet its performance specification if the input clockhigh and low times are maintained within the range(20/80% ratio).

High speed, high performance ADCs such as the AD-C08D1520 require a very stable input clock signal with mini-mum phase noise or jitter. ADC jitter requirements are defined

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ADC08D1520QMLby the ADC resolution (number of bits), maximum ADC inputfrequency and the input signal amplitude relative to the ADCinput full scale range. The maximum jitter (the sum of the jitterfrom all sources) allowed to prevent a jitter-induced reductionin SNR is found to be

tJ(MAX) = (VIN(P-P)/VINFSR) x (1/(2(N+1) x π x fIN))

where tJ(MAX) is the rms total of all jitter sources in seconds,VIN(P-P) is the peak-to-peak analog input signal, VINFSR is thefull-scale range of the ADC, \"N\" is the ADC resolution in bitsand fIN is the maximum input frequency, in Hertz, at the ADCanalog input.

Note that the maximum jitter described above is the RSS sumof the jitter from all sources, including that in the ADC inputclock, that added by the system to the ADC input clock andinput signals and that added by the ADC itself. Since the ef-fective jitter added by the ADC is beyond user control, the bestthe user can do is to keep the sum of the externally addedinput clock jitter and the jitter added by the analog circuitry tothe analog signal to a minimum.

Input clock amplitudes above those specified in the ConverterElectrical Characteristics may result in increased input offsetvoltage. This would cause the converter to produce an outputcode other than the expected 127/128 when both input pinsare at the same potential.

2.5 CONTROL PINS

Six control pins (without the use of the serial interface) providea wide range of possibilities in the operation of the AD-C08D1520 and facilitate its use. These control pins provideFull-Scale Input Range setting, Self Calibration, Output EdgeSynchronization choice, LVDS Output Level choice and aPower Down feature.

2.5.1 Full-Scale Input Range Setting

The input full-scale range can be selected with the FSR con-trol input (pin 14) in the Normal Mode of operation. The inputfull-scale range is specified as VIN in the Converter ElectricalCharacteristics. In the Extended Control Mode, the input full-scale range may be programmed using the Full-Scale AdjustVoltage register. See 2.3 THE ANALOG INPUT for more in-formation.

2.5.2 Calibration

The ADC08D1520 calibration must be run to achieve speci-fied performance. The calibration must be initiated by theuser. The calibration procedure is exactly the same whetherthere is an input clock present upon power up or if the clockbegins some time after application of power. The CalRun out-put indicator is high while a calibration is in progress. Notethat the DCLK outputs are not active during a calibration cycleby default, therefore it is not recommended for use as a sys-tem clock. The DCLK outputs are continuously present at theoutput only when the Resistor Trim Disable is activated.2.5.2.1 Initiating Calibration

A calibration may be run at any time in both the Non-DES andDES Modes. After power-up, we recommend that the part becalibrated with the Resistor Trim Disable inactive once thepower supplies have stabilized and the temperature of thechip has stabilized. When a calibration is run with the ResistorTrim Disable inactive, both the ADC and the input terminationresistor are calibrated. However, since the input terminationresistance changes only marginally with temperature, the us-er has the option to disable the input termination resistorcalibration for subsequent calibrations, which will guaranteethat the DCLK is continuously present at the output. The Re-41

sistor Trim Disable can be programmed in the ExtendedConfiguration register (Addr: 9h) when in the Extended Con-trol Mode. Refer to Extended Configuration Register for reg-ister programming information.

As dynamic performance changes slightly with junction tem-perature, a calibration may be executed to bring the perfor-mance of the ADC in line. Two methods can be used initiatea calibration. The first method is to hold the CAL pin low forat least tCAL_L input clock cycles, then hold it high for at leastanother tCAL_H input clock cycles. The second method is toprogram the CAL bit in the Calibration register while in Ex-tended Control Mode. The functionality of the CAL bit isexactly the same as using the CAL pin. The CAL bit must beprogrammed to 0b for a minimum of tCAL_Linput clock cyclesand then programmed to 1b for a minimum of tCAL_H inputclock cycles to initiate a calibration cycle. The CalRun signalshould be monitored to determine when the calibration cyclehas completed. The CalRun pin will become a logic high in-dicating an active calibration cycle regardless of whichmethod was used to initiate the calibration cycle. Note that theDCLK outputs are not active during a calibration cycle; there-fore, it is not recommended for use as a system clock.

The minimum number of tCAL_L and tCAL_H input clock cyclesequences are required to ensure that random noise does notcause a calibration to begin when it is not desired. As men-tioned in 1.1 OVERVIEW, for best performance, a calibrationshould be performed 20 seconds or more after power up andrepeated when the operating temperature changes signifi-cantly relative to the specific system design performancerequirements. Dynamic performance changes slightly with in-creasing junction temperature and can be easily corrected byperforming a calibration.

2.5.3 Output Edge Synchronization

DCLK signals are available to help latch the converter outputdata into external circuitry. The output data can be synchro-nized with either edge of these DCLK signals. That is, theoutput data transition can be set to occur with either the risingedge or the falling edge of the DCLK signal, so that eitheredge of that DCLK signal can be used to latch the output datainto the receiving circuit.

When OutEdge (pin 4) is high, the output data is synchronizedwith (changes with) the rising edge of the DCLK+ (pin 82).When OutEdge is low, the output data is synchronized withthe falling edge of DCLK+.

At the very high speeds of which the ADC08D1520 is capable,slight differences in the lengths of the DCLK and data linescan mean the difference between successful and erroneousdata capture. The OutEdge pin is used to capture data on theDCLK edge that best suits the application circuit and layout.2.5.4 LVDS Output Level Control

The output level can be set to one of two levels with OutV(pin3). The strength of the output drivers is greater with OutVhigh. With OutV low there is less power consumption in theoutput drivers, but the lower output level means decreasednoise immunity.

For short LVDS lines and low noise systems, satisfactory per-formance may be realized with the OutV input low. If the LVDSlines are long and/or the system in which the ADC08D1520is used is noisy, it may be necessary to tie the OutV pin high.2.5.5 Dual Edge Sampling

The Dual Edge Sampling (DES) feature causes one of the twoinput pairs to be routed to both ADCs. The other input pair isdeactivated. One of the ADCs samples the input signal on the

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ADC08D1520QMLrising input clock edge (duty cycle corrected), the other sam-ples the input signal on the falling input clock edge (duty cyclecorrected). If the device is in the 1:4 Demux DES Mode, theresult is an output data rate 1/4 that of the interleaved samplerate which is twice the input clock frequency. Data is present-ed in parallel on all four output buses in the following order:DQd, DId, DQ, DI. If the device is the Non-Demultiplex outputmode, the result is an output data rate 1/2 that of the inter-leaved sample rate. Data is presented in parallel on twooutput buses in the following order: DQ, DI.

To use this feature in the Non-Extended Control Mode, tie pin127 to VA/2 and the signal at the I- channel input will be sam-pled by both converters.

In the Extended Control Mode, either input may be used fordual edge sampling. See 1.1.5.1 Dual-Edge Sampling.2.5.6 Power Down Feature

The Power Down pins (PD and PDQ) allow the ADC08D1520to be entirely powered down (PD) or the Q- Channel channelto be powered down and the I- Channel to remain active. See1.1.7 Power Down for details on the power down feature.The digital data (+/-) output pins are put into a high impedancestate when the PD pin for the respective channel is high. Uponreturn to normal operation, the pipeline will contain meaning-less information and must be flushed.

2.6 THE DIGITAL OUTPUTS

The ADC08D1520 demultiplexes the output data of each ofthe two ADCs on the die onto two LVDS output buses (totalof four buses, two for each ADC). For each of the two con-verters, the results of successive conversions started on theodd falling edges of the CLK+ pin are available on one of thetwo LVDS buses, while the results of conversions started onthe even falling edges of the CLK+ pin are available on theother LVDS bus. This means that, the word rate at each LVDSbus is 1/2 the ADC08D1520 input clock rate and the two bus-es must be multiplexed to obtain the entire 1.5 GSPS con-version result.

Since the minimum recommended input clock rate for thisdevice is 200 MSPS (Non DES Mode), the effective rate canbe reduced to as low as 100 MSPS by using the results avail-able on just one of the two LVDS buses and a 200 MHz inputclock, decimating the 200 MSPS data by two.

There is one LVDS output clock pair (DCLK+/-) available foruse to latch the LVDS outputs on all buses. Whether the datais sent at the rising or falling edge of DCLK is determined bythe sense of the OutEdge pin, as described in 2.5.3 OutputEdge Synchronization.

DDR (Double Data Rate) clocking can also be used. In thismode a word of data is presented with each edge of DCLK,reducing the DCLK frequency to 1/4 the input clock frequency.See the Timing Diagram section for details.

The OutV pin is used to set the LVDS differential output levels.See 2.5.4 LVDS Output Level Control.

The output format is Offset Binary. Accordingly, a full-scaleinput level with VIN+ positive with respect to VIN− will producean output code of all ones, a full-scale input level with VIN−positive with respect to VIN+ will produce an output code of all

zeros and when VIN+ and VIN− are equal, the output code willvary between codes 127 and 128.

2.7 POWER CONSIDERATIONS

A/D converters draw sufficient transient current to corrupttheir own power supplies if not adequately bypassed. A 33 µFcapacitor should be placed within an inch (2.5 cm) of the A/Dconverter power pins. A 0.1 µF capacitor should be placed asclose as possible to each VA pin, preferably within one-halfcentimeter. Leadless chip capacitors are preferred becausethey have low lead inductance.

The VA and VDR supply pins should be isolated from eachother to prevent any digital noise from being coupled into theanalog portions of the ADC. A ferrite choke, such as the JWMiller FB20009-3B, is recommended between these supplylines when a common source is used for them.

As is the case with all high speed converters, the AD-C08D1520 should be assumed to have little power supplynoise rejection. Any power supply used for digital circuitry ina system where a lot of digital power is being consumedshould not be used to supply power to the ADC08D1520. TheADC supplies should be the same supply used for other ana-log circuitry, if not a dedicated supply.

2.7.1 Supply Voltage

The ADC08D1520 is specified to operate with a supply volt-age of 1.9V ±0.1V. It is very important to note that, while thisdevice will function with slightly higher supply voltages, thesehigher supply voltages may reduce product lifetime.

No pin should ever have a voltage on it that is in excess of thesupply voltage or below ground by more than 150 mV, noteven on a transient basis. This can be a problem upon appli-cation of power and power shut-down. Be sure that the sup-plies to circuits driving any of the input pins, analog or digital,do not come up any faster than does the voltage at the AD-C08D1520 power pins.

The Absolute Maximum Ratings should be strictly observed,even during power up and power down. A power supply thatproduces a voltage spike at turn-on and/or turn-off of powercan destroy the ADC08D1520. The circuit of Figure 15 willprovide supply overshoot protection.

Many linear regulators will produce output spiking at power-on unless there is a minimum load provided. Active devicesdraw very little current until their supply voltages reach a fewhundred millivolts. The result can be a turn-on spike that candestroy the ADC08D1520, unless a minimum load is providedfor the supply. The 100Ω resistor at the regulator output pro-vides a minimum output current during power-up to ensurethere is no turn-on spiking.

In the circuit of Figure 15, an LM317 linear regulator is satis-factory if its input supply voltage is 4V to 5V . If a 3.3V supplyis used, an LM1086 linear regulator is recommended.

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FIGURE 15. Non-Spiking Power Supply

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ADC08D1520QMLThe output drivers should have a supply voltage, VDR, that iswithin the range specified in the Operating Ratings table. Thisvoltage should not exceed the VA supply voltage.

If the power is applied to the device without an input clocksignal present, the current drawn by the device might be be-low 200 mA. This is because the ADC08D1520 gets resetthrough clocked logic and its initial state is unknown. If thereset logic comes up in the \"on\" state, it will cause most of theanalog circuitry to be powered down, resulting in less than100 mA of current draw. This current is greater than the powerdown current because not all of the ADC is powered down.The device current will be normal after the input clock is es-tablished.

2.7.2 Thermal Management

The ADC08D1520 is capable of impressive speeds and per-formance at very low power levels for its speed. However, thepower consumption is still high enough to require attention tothermal management. For reliability reasons, the die temper-ature should be kept to a maximum of 150°C. That is, TA(ambient temperature) plus ADC power consumption timesθJA (junction to ambient thermal resistance) should not ex-ceed 150°C.

Please note that the following are recommendations formounting this device onto a PCB. This should be consideredthe starting point in PCB and assembly process development.It is recommended that the process be developed based uponpast experience in package mounting.

The bottom of the package of the ADC08D1520 provides theprimary heat removal path as well as excellent electricalgrounding to the printed circuit board. The land pattern designfor lead attachment to the PCB should be the same as for aconventional LQFP, but the bottom of the package must beattached to the board to remove the maximum amount of heatfrom the package, as well as to ensure best product para-metric performance.

To maximize the removal of heat from the package, a thermalland pattern must be incorporated on the PC board within thefootprint of the package. The bottom of the device must besoldered down to ensure adequate heat conduction out of thepackage. The land pattern for this exposed pad should be aslarge as the 600 x 600 mil bottom of the package and be lo-cated such that the bottom of the device is entirely over thatthermal land pattern. This thermal land pattern should beelectrically connected to ground.

Since a large aperture opening may result in poor release, theaperture opening should be subdivided into an array of small-er openings, similar to the land pattern of Figure 16.

To minimize junction temperature, it is recommended that asimple heat sink be built into the PCB. This is done by includ-ing a copper area of about 2.25 square inches (14.52 squarecm) on the opposite side of the PCB. This copper area maybe plated or solder coated to prevent corrosion, but shouldnot have a conformal coating, which could provide some ther-mal insulation. Thermal vias should be used to connect thesetop and bottom copper areas. These thermal vias act as \"heatpipes\" to carry the thermal energy from the device side of theboard to the opposite side of the board where it can be moreeffectively dissipated. The use of approximately 100 thermalvias is recommended. Use of a higher weight copper on theinternal ground plane is recommended, (i.e. 2OZ instead of1OZ, for thermal considerations only.

The thermal vias should be placed on a 61mil grid spacingand have a diameter of 15 mil typically. These vias should bebarrel plated to avoid solder wicking into the vias during thesoldering process as this wicking could cause voids in thesolder between the package exposed pad and the thermalland on the PCB. Such voids could increase the thermal re-sistance between the device and the thermal land on theboard, which would cause the device to run hotter.

If it is desired to monitor die temperature, a temperature sen-sor may be mounted on the heat sink area of the board nearthe thermal vias. Allow for a thermal gradient between thetemperature sensor and the ADC08D1520 die of θJ-PAD timestypical power consumption.

2.7.3 TEMPERATURE SENSOR DIODE

The ADC08D1520 has an on-die temperature diode connect-ed to pins Tdiode+/- which may be used to monitor the dietemperature. National also provides a family of temperaturesensors for this application which monitor different numbersof external devices, See Table 9

TABLE 9. Temperature Sensor RecommendationNumber of ExternalDevices Monitored

124

Recommended Temperature

Sensor

LM95235LM95213LM95214

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FIGURE 16. Recommended Package Land Pattern

The LM95235/13/14 is an 11-bit digital temperature sensorwith a 2-wire System Management Bus (SMBus) interfacethat can monitor the temperature of one/two/four remotediodes as well as its own temperature. The LM95235/13/14can be used to accurately monitor the temperature of up toone/two/four external devices such as the ADC08D1520, aFPGA, other system components, and the ambient tempera-ture.

The LM95235/13/14 reports temperature in two different for-mats for +127.875°C range and 0°/255°C range. TheLM95235/13/14 has a Sigma-Delta ADC core which providesthe first level of noise immunity. For improved performance ina noise environment, the LM9535/13/14 includes pro-grammable digital filters for Remote Diode temperature read-ings. When the digital filters are invoked, the resolution for theRemote Diode readings increases to 0.03125°C. For maxi-mum flexibility and best accuracy, the LM95235/13/14 in-cludes offset registers that allow calibration of other diodetypes.

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ADC08D1520QMLDiode fault detection circuitry in the LM95235/13/14 can de-tect the absence or fault state of a remote diode: whether D+is shorted to the power supply, D- or ground, or floating.In the following typical application, the LM95213 is used tomonitor the temperature of an ADC08D1520 as well as a FP-GA. See Figure 17

2.9 DYNAMIC PERFORMANCE

The ADC08D1520 is a.c. tested and its dynamic performanceis guaranteed. To meet the published specifications and avoidjitter-induced noise, the clock source driving the CLK inputmust exhibit low rms jitter. The allowable jitter is a function ofthe input frequency and the input signal level, as described in2.4 THE CLOCK INPUTS.

It is good practice to keep the ADC input clock line as shortas possible, to keep it well away from any other signals andto treat it as a transmission line. Other signals can introducejitter into the input clock signal. The clock signal can also in-troduce noise into the analog path if not isolated from thatpath.

Best dynamic performance is obtained when the exposed padat the back of the package has a good connection to ground.This is because this path from the die to ground is a lowerimpedance than offered by the package pins.

2.10 USING THE SERIAL INTERFACE

The ADC08D1520 may be operated in the Non-ExtendedControl (non-Serial Interface) Mode or in the extended controlmode. Table 10 and Table 11 describe the functions of pins3, 4, 14 and 127 in the Non-Extended Control Mode and theExtended Control Mode, respectively.

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FIGURE 17. Typical Temperature Sensor Application2.8 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essen-tial to ensure accurate conversion. A single ground planeshould be used, instead of splitting the ground plane into ana-log and digital areas.

Since digital switching transients are composed largely ofhigh frequency components, the skin effect tells us that totalground plane copper weight will have little effect upon thelogic-generated noise. Total surface area is more importantthan is total ground plane volume. Coupling between the typ-ically noisy digital circuitry and the sensitive analog circuitrycan lead to poor performance that may seem impossible toisolate and remedy. The solution is to keep the analog cir-cuitry well separated from the digital circuitry.

High power digital components should not be located on ornear any linear component or power supply trace or plane thatservices analog or mixed signal components as the resultingcommon return current path could cause fluctuation in theanalog input “ground” return of the ADC, causing excessivenoise in the conversion result.

Generally, we assume that analog and digital lines shouldcross each other at 90° to avoid getting digital noise into theanalog path. In high frequency systems, however, avoidcrossing analog and digital lines altogether. The input clocklines should be isolated from ALL other lines, analog ANDdigital. The generally accepted 90° crossing should be avoid-ed as even a little coupling can cause problems at highfrequencies. Best performance at high frequencies is ob-tained with a straight signal path.

The analog input should be isolated from noisy signal tracesto avoid coupling of spurious signals into the input. This isespecially important with the low level drive required of theADC08D1520. Any external component (e.g., a filter capaci-tor) connected between the converter's input and groundshould be connected to a very clean point in the analogground plane. All analog circuitry (input amplifiers, filters, etc.)should be separated from any digital components.

2.10.1 Non-Extended Control Mode Operation

Non-extended Control Mode operation means that the SerialInterface is not active and all controllable functions are con-trolled with various pin settings. Pin 41 is the primary controlof the extended control enable function. When pin 41 is logichigh, the device is in the Non-Extended Control Mode. If pin41 is tied to VA/2 and pin 52 connected to VA/2 or logic high,the extended control enable function is controlled by pin 14.The device has functions which are pin programmable whenin the Non-Extended Control Mode. An example is the full-scale range is controlled in the Non-Extended Control Modeby setting pin 14 high or low. Table 10 indicates the pin func-tions of the ADC08D1520 in the Non-Extended Control Mode.TABLE 10. Non-Extended Control Mode Operation

(Pin 41 VA/2 and Pin 52 VA/2 or Logic High)Pin3412714

LowReduced VODOutEdge = Neg

N/AReduced VIN

HighNormal VODOutEdge = Pos

N/ANormal VIN

VA/2n/aDDRDESExtendedControlMode

Pin 3 can be either high or low in the Non-Extended ControlMode. See 1.2 NON-EXTENDED CONTROL/EXTENDEDCONTROL for more information.

Pin 4 can be high or low in the Non-Extended Control Mode.In the Non-Extended Control Mode, pin 4 high or low definesthe edge at which the output data transitions. See 2.5.3 Out-put Edge Synchronization for more information. If this pin istied to VA/2, the output clock (DCLK) is a DDR (Double DataRate) clock (see 1.1.5.3 Double Data Rate) and the outputedge synchronization is irrelevant since data is clocked outon both DCLK edges.

When in Normal Mode, Pin 127 must be tied high. If pin 127is tied to VA/2, the converter performs dual edge sampling(DES).

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ADC08D1520QMLTABLE 11. Extended Control Mode Operation (Pin 41

Logic Low and Pin 52 VA/2 or Logic High)

Pin34127

FunctionSCLK (Serial Clock)SDATA (Serial Data)SCS (Serial Interface Chip Select)2.11 COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the powersupply rails. For device reliability, no input should go morethan 150 mV below the ground pins or 150 mV above thesupply pins. Exceeding these limits on even a transient basismay not only cause faulty or erratic operation, but may impairdevice reliability. It is not uncommon for high speed digitalcircuits to exhibit undershoot that goes more than a volt belowground. Controlling the impedance of high speed lines andterminating these lines in their characteristic impedanceshould control overshoot.

Care should be taken not to overdrive the inputs of the AD-C08D1520. Such practice may lead to conversion inaccura-cies and even to device damage.

Driving the VBG pin to change the reference voltage. Asmentioned in 2.2 THE REFERENCE VOLTAGE, the refer-

ence voltage is intended to be fixed to provide one of twodifferent full-scale values (650 mVP-P and 870 mVP-P). Overdriving this pin will not change the full scale value, but can beused to change the LVDS common mode voltage from 0.8Vto 1.2V by tying the VBG pin to VA.

Driving the clock input with an excessively high levelsignal. The ADC input clock level should not exceed the leveldescribed in the Operating Ratings Table or the input offsetcould change.

Inadequate input clock levels. As described in 2.4 THECLOCK INPUTS, insufficient input clock levels can result inpoor performance. Excessive input clock levels could resultin the introduction of an input offset.

Using a clock source with excessive jitter, using an ex-cessively long input clock signal trace, or having othersignals coupled to the input clock signal trace. This willcause the sampling interval to vary, causing excessive outputnoise and a reduction in SNR performance.

Failure to provide adequate heat removal. As described in2.7.2 Thermal Management, it is important to provide ade-quate heat removal to ensure device reliability. This can bedone either with adequate air flow or the use of a simple heatsink built into the board. The backside pad should be ground-ed for best performance.

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ADC08D1520QMLRevision History

Date Released01/09/0803/05/0804/21/09

Revision

ABC

Section

Initial Release, New ProductWhole data sheet

Features and Key Specifications, ElectricalSection, Table 3, Paragraph 1.3 The SerialInterface, Table 5, Paragraph 1.4

Configuration Register, Paragraph 2.7.3.

Changes

New Product Data Sheet, Released at Edit 16Edit clarification Updates, Revision A will beArchived.

Moved Radiation reference from Key

Specifications to Features. Combined typical tableinto main electrical table. Correction to paragraphunder Table 3, Table 5 Header. Added New

paragraph to 1.3, 1.4 Configuration Register and2.7.3 paragraph. Revision B will be Archived.

05/28/09D

Absolute Maximum Ratings and OperatingAbsolute Maximum Ratings added Voltage on VIN

+, V-. Operating Ratings changed V+, V-RatingsINININ

Voltage Range. Revision C will be Archived.Ordering Information, Electrical Section,Note Section.

Removed Non Rad NSID, Added parameters toDC: Digital Control Pin Characteristics, VIH andVIL tighten the limits. AC Section, Radiation Tableand Note 15. Revision D will be Archived.

06/08/09E

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ADC08D1520QMLPhysical Dimensions inches (millimeters) unless otherwise noted

NOTES: UNLESS OTHERWISE SPECIFIED

REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB.

128-Lead Ceramic Quad(Gold Lead Finish)

NS Package Number EL128A

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ADC08D1520QML Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D ConverterNotes

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