OPA832SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004Low-Power, Single-Supply, Fixed-GainVideo Buffer AmplifierFEATURESDHIGH BANDWIDTH: 80MHz (G = +2)DLOW SUPPLY CURRENT: 3.9mADFLEXIBLE SUPPLY RANGE:DDDDDDESCRIPTIONThe OPA832 is a low-power, high-speed, fixed-gain amplifierdesigned to operate on a single +3.3V or +5V supply.Operation on ±5V or +10V supplies is also supported. Theinput range extends below ground and to within 1V of thepositive supply. Using complementary common-emitteroutputs provides an output swing to within 30mV of groundand 130mV of the positive supply. The high output drivecurrent and low differential gain and phase errors also makeit ideal for single-supply consumer video products.Low distortion operation is ensured by the high gainbandwidth product (200MHz) and slew rate (850V/µs), makingthe OPA832 an ideal input buffer stage to 3V and 5V CMOSconverters. Unlike other low-power, single-supply amplifiers,distortion performance improves as the signal swing isdecreased. A low 9.3nV/√Hz input voltage noise supportswide dynamic range operation.The OPA832 is available in an industry-standard SO-8package. The OPA832 is also available in an ultra-smallSOT23-5 package. For gains other than +1, −1, or +2,consider using the OPA830.+2.8V to +11V Single Supply±1.4V to ±5.5V Dual SupplyINPUT RANGE INCLUDES GROUND ONSINGLE SUPPLY4.9VPP OUTPUT SWING ON +5V SUPPLYHIGH SLEW RATE: 350V/µsecLOW INPUT VOLTAGE NOISE: 9.3nV/√HzAVAILABLE IN AN SOT23 PACKAGEAPPLICATIONSDDDDSINGLE-SUPPLY VIDEO LINE DRIVERSCCD IMAGING CHANNELSLOW-POWER ULTRASOUNDPORTABLE CONSUMER ELECTRONICSRELATED PRODUCTSDESCRIPTIONMedium SpeedMedium Speed,Fixed GainSINGLESOPA830—DUALSOPA2830OPA2832TRIPLES—OPA3832QUADSOPA4830—+3.3VVideoDACVI976Ω75ΩLARGE−SIGNALBANDWIDTH(1VPPATMATCHEDLOAD)080.6ΩIIOPA83275ΩLoad400ΩVO400ΩVIVO−3Gain(dB)=1V/V−6−9Single-Supply, Low-Cost Video Line Driver110Frequency(MHz)100Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.All trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date. Productsconform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.Copyright 2003−2004, Texas Instruments Incorporatedwww.ti.comOPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004ABSOLUTE MAXIMUM RATINGS(1)Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12VDCInternal Power Dissipation. . . . . . . . . See Thermal CharacteristicsDifferential Input Voltage(2). . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2VInput Voltage Range. . . . . . . . . . . . . . . . . . . . . −0.5V to +VS + 0.3VStorage Temperature Range: D, DBV. . . . . . . . . −40°C to +125°CLead Temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . +300°CJunction Temperature (TJ). . . . . . . . . . . . . . . . . . . . . . . . . . . +150°CESD Rating:Human Body Model (HBM). . . . . . . . . . . . . . . . . . . . . . . 2000VCharge Device Model (CDM). . . . . . . . . . . . . . . . . . . . . 1500VMachine Model (MM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V(1)Stresses above these ratings may cause permanent damage.Exposure to absolute maximum conditions for extended periodsmay degrade device reliability. These are stress ratings only, andfunctional operation of the device at these or any other conditionsbeyond those specified is not supported.(2)Noninverting input to internal inverting node.This integrated circuit can be damaged by ESD. TexasInstruments recommends that all integrated circuits behandled with appropriate precautions. Failure to observeproper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation tocomplete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.PACKAGE/ORDERING INFORMATION(1)PRODUCTOPA832″OPA832″PACKAGE-LEADSO-8 Surface-Mount″SOT23-5″PACKAGEDESIGNATORD″DBV″SPECIFIEDTEMPERATURERANGE−40°C to +85°C″−40°C to +85°C″PACKAGEMARKINGOPA832″A74″ORDERINGNUMBEROPA832IDOPA832IDROPA832IDBVTOPA832IDBVRTRANSPORTMEDIA, QUANTITYRails, 100Tape and Reel, 2500Tape and Reel, 250Tape and Reel, 3000(1)For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.PIN CONFIGURATIONSOutput15+VS−VSNCInvertingInputNoninvertingInput−VS1400Ω234SO−8NC=NoConnection765+VS400Ω8NCNoninvertingInput2400Ω400Ω43SOT23−5InvertingInputOutput5NC423A74PinOrientation/PackageMarking12OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C.At TA = 25°C, G = +2, and RL = 150Ω to GND, unless otherwise noted (see Figure 3).OPA832ID, IDBVTYPPARAMETERAC PERFORMANCE (see Figure 3)Small-Signal BandwidthPeaking at a Gain of +1Slew RateRise TimeFall TimeSettling Time to 0.1%Harmonic Distortion2nd-Harmonic3rd-HarmonicInput Voltage NoiseInput Current NoiseNTSC Differential GainNTSC Differential PhaseDC PERFORMANCE(4)Gain ErrorInternal RF and RGMaximumMinimumAverage DriftInput Offset VoltageAverage Offset Voltage DriftInput Bias CurrentInput Bias Current DriftInput Offset CurrentInput Offset Current DriftINPUTNegative Input Voltage RangePositive Input Voltage RangeInput ImpedanceDifferential ModeCommon-ModeOUTPUTOutput Voltage SwingCurrent Output, SinkingCurrent Output, SourcingShort-Circuit CurrentClosed-Loop Output ImpedancePOWER SUPPLYMinimum Operating VoltageMaximum Operating VoltageMaximum Quiescent CurrentMinimum Quiescent CurrentPower-Supply Rejection Ratio (PSRR)THERMAL CHARACTERISTICSSpecification: ID, IDBVThermal ResistanceDSO-8DBVSOT23-5RL = 1kΩ to GNDRL = 150Ω to GNDCONDITIONSG = +2, VO ≤ 0.5VPPG = −1, VO ≤ 0.5VPPVO ≤ 0.5VPPG = +2, 2V Step0.5V Step0.5V StepG = +2, 1V StepVO = 2VPP, 5MHzRL = 150ΩRL = 500ΩRL = 150ΩRL = 500Ωf > 1MHzf > 1MHzRL = 150ΩRL = 150ΩG = +2G = −1+25°C80994.23504..945−−66−57−739.22.20.100.16±0.3±0.2400400±1.4—+5.5±0.1—−5.43.210 2.1400 1.2±4.9±4.685851200.2±1.4—4.2.2568−40 to +85125150±4.8±4.56565±4.75±4.456060±4.75±4.45555MIN/MAX OVER TEMPERATURE+25°C(1)55572300°C to70°C(2)56230−40°C to+85°C(2)56220UNITSMHzMHzdBV/µsnsnsnsdBcdBcdBcdBcnV/√HzpA/√Hz%°%%ΩΩ%/°CmVµV/°CµAnA/°CµAnA/°CVVkΩ pFkΩ pFVVmAmAmAΩVVmAmAdB°C°C/W°C/WMIN/MAXminmintypminmaxmaxmaxmaxmaxmaxmaxmaxmaxtyptypminmaxmaxmaxmaxmaxmaxmaxmaxmaxmaxmaxmintyptypmaxmaxminmintyptypminmaxmaxminmintyptyptypTESTLEVEL(3)BBCBBBBBBBBBBCCABAABABABABBACCAAAACCBAAAACCC−60−63−50−−60−63−49−61−60−63−48−57±1.5±1.55345±7+10±1.5±1.6±1.60340±0.1±8±20+12±12±2±10−5.03.0±1.7±1.7462338±0.1±8.5±20+13±12±2.5±10−4.92.9−5.23.1Output Shorted to Either SupplyG = +2, f ≤ 100kHzVS = ±5VVS = ±5VInput-Referred±5..74.063±5.55.33.662±5.55.93.361(1)Junction temperature = ambient for +25°C specifications.(2)Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over temperature specifications.(3)Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typicalvalue only for information.(4)Current is considered positive out of node.3OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits are tested at +25°C.At TA = 25°C, G = +2, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 1).OPA832ID, IDBVTYPPARAMETERAC PERFORMANCE (see Figure 1)Small-Signal BandwidthPeaking at a Gain of +1Slew RateRise TimeFall TimeSettling Time to 0.1%Harmonic Distortion2nd-Harmonic3rd-HarmonicInput Voltage NoiseInput Current NoiseNTSC Differential GainNTSC Differential PhaseDC PERFORMANCE(4)Gain ErrorInternal RF and RG, MaximumMinimumAverage DriftInput Offset VoltageAverage Offset Voltage DriftInput Bias CurrentInput Bias Current DriftInput Offset CurrentInput Offset Current DriftINPUTLeast Positive Input VoltageMost Positive Input VoltageInput ImpedanceDifferential-ModeCommon-ModeOUTPUTLeast Positive Output VoltageMost Positive Output VoltageCurrent Output, SourcingCurrent Output, SinkingShort-Circuit Output CurrentClosed-Loop Output ImpedancePOWER SUPPLYMinimum Operating VoltageMaximum Operating VoltageMaximum Quiescent CurrentMinimum Quiescent CurrentPower-Supply Rejection Ratio (PSRR)THERMAL CHARACTERISTICSSpecification: ID, IDBVThermal ResistanceDSO-8DBVSOT23-5(1)(2)MIN/MAX OVER TEMPERATURE+25°C(1)56602300°C to70°C(2)5558223−40°C to+85°C(2)5558223UNITSMHzMHzdBV/µsnsnsnsdBcdBcdBcdBcnV/√HzpA/√Hz%°%%ΩΩ%/°CmVµV/°CµAnA/°CµAnA/°CVVkΩ pFkΩ pF0.160.34.84.660600.180.3..555550.200.404.44.45252VVVVmAmAmAΩVVmAmAdB°C°C/W°C/WMIN/MAXminmintypminmaxmaxmaxmaxmaxmaxmaxmaxmaxtyptypminmaxmaxmaxmaxmaxmaxmaxmaxmaxmaxmaxmintyptypmaxmaxminminminmintyptyptypmaxmaxminmintyptyptypTESTLEVEL(3)BBCBBBBBBBBBBCCABAABABABABBBCCAAAAAACCCAAAACCCCONDITIONSG = +2, VO ≤ 0.5VPPG = −1, VO ≤ 0.5VPPVO ≤ 0.5VPPG = +2, 2V Step0.5V Step0.5V StepG = +2, 1V StepVO = 2VPP, 5MHzRL = 150ΩRL = 500ΩRL = 150ΩRL = 500Ωf > 1MHzf > 1MHzRL = 150ΩRL = 150ΩG = +2G = −1+25°C921034.23484.34..6−59−62−56−729.32.30.110.14±0.3±0.2400400±0.5—5.5±0.1—−0.53.310 2.1400 1.2−56−59−50−65−56−59−49−62−55−59−47−58±1.5±1.55345±5+10±1.5VCM = 2.0VVCM = 2.0V±1.6±1.603400.1±6±20+12±12±2±1003.1±1.7±1.74623380.1±6.5±20+13±12±2.5±10+0.13.0−0.23.2RL = 1kΩ to 2.0VRL = 150Ω to 2.0VRL = 1kΩ to 2.0VRL = 150Ω to 2.0VOutput Shorted to Either SupplyG = +2, f ≤ 100kHz0.030.184.944.8680801000.2+2.8—3.93.966−40 to +85125150VS = +5VVS = +5VInput-Referred+114.13.761+114.83.560+115.53.259Junction temperature = ambient for +25°C specifications.Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over temperature.(3)Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value onlyfor information.(4)Current is considered positive out of node.4OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004ELECTRICAL CHARACTERISTICS: VS = +3.3V Boldface limits are tested at +25°C.At TA = 25°C, G = +2, and RL = 150Ω to VCM = 0.75V, unless otherwise noted (see Figure 2).OPA832ID, IDBVTYPPARAMETERAC PERFORMANCE (see Figure 2)Small-Signal BandwidthPeaking at a Gain of +1Slew RateRise TimeFall TimeSettling Time to 0.1%Harmonic Distortion2nd-Harmonic3rd-HarmonicInput Voltage NoiseInput Current NoiseDC PERFORMANCE(4)Gain ErrorInternal RF and RGMaximumMinimumAverage DriftInput Offset VoltageAverage Offset Voltage DriftInput Bias CurrentInput Bias Current DriftInput Offset CurrentInput Offset Current DriftINPUTLeast Positive Input VoltageMost Positive Input VoltageInput Impedance, Differential-ModeCommon-ModeOUTPUTLeast Positive Output VoltageMost Positive Output VoltageCurrent Output, SourcingCurrent Output, SinkingShort-Circuit Output CurrentClosed-Loop Output ImpedancePOWER SUPPLYMinimum Operating VoltageMaximum Operating VoltageMaximum Quiescent CurrentMinimum Quiescent CurrentPower-Supply Rejection Ratio (PSRR)THERMAL CHARACTERISTICSSpecification: ID, IDBVThermal ResistanceDSO-8DBVSOT23-5RL = 1kΩ to 0.75VRL = 150Ω to 0.75VRL = 1kΩ to 0.75VRL = 150Ω to 0.75VCONDITIONSG = +2, VO ≤ 0.5VPPG = −1, VO ≤ 0.5VPPVO ≤ 0.5VPP1V Step0.5V Step0.5V Step1V Step5MHzRL = 150ΩRL = 500ΩRL = 150ΩRL = 500Ωf > 1MHzf > 1MHzG = +2G = −1+25°C951034.217044.248−71−74−66−699.42.4±0.3±0.2400400±1MIN/MAX OVERTEMPERATURE+25°C(1)59631150°C to70°C(2)5761115UNITSMHzMHzdBV/µsnsnsnsdBcdBcdBcdBcnV/√HzpA/√Hz%%ΩΩ%/°CmVµV/°CµAnA/°CµAnA/°CVVkΩ pFkΩ pFVVVVmAmAmAΩVVmAmAdB°C°C/W°C/WMIN/MAXminmintypminmaxmaxmaxmaxmaxmaxmaxmaxmaxminmaxmaxmaxmaxmaxmaxmaxmaxmaxmaxmaxmintyptypmaxmaxminminminmintyptyptypmaxmaxmintyptyptyptypTESTLEVEL(3)BBCBBBBBBBBBBABAABABABABBBCCBBBBAACCCAAACCCC−−70−60−66−62−66−55−62±1.5±1.55345±7+10±1.5±1.6±1.603400.1±8±20+12±12±2±10−0.21.3VCM = 0.75VVCM = 0.75V—5.5±0.1—−0.51.510 2.1400 1.20.030.1333535800.2+2.8—3.83.860−40 to +85125150−0.31.40.160.32.82.825250.180.352.62.62020Output Shorted to Either SupplySee Figure 2, f < 100kHzVS = +3.3VVS = +3.3VInput-Referred+114.03.4+114.73.2(1)Junction temperature = ambient for +25°C specifications.(2)Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over temperature.(3)Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only(4)Current is considered positive out of node.for information.5OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004TYPICAL CHARACTERISTICS: VS = ±5VAt TA = 25°C, G = +2, and RL = 150Ω to GND, unless otherwise noted (see Figure 3).SMALL−SIGNALFREQUENCYRESPONSE30NormalizedGain(dB)−3G=−1−6−9−12−15110Frequency(MHz)100500VO=0.2VPPRL=150ΩNormalizedGain(dB)30−3−6−9−12−151LARGE−SIGNALFREQUENCYRESPONSERL=150ΩG=+2V/VVO=1VPPVO=0.5VPPVO=4VPPVO=2VPP10Frequency(MHz)100400G=+2SMALL−SIGNALPULSERESPONSE150100500−50−100−150Time(10ns/div)G=+2V/VRL=150ΩVO=0.2VPP1.5OutputVoltage(500mV/div)1.00.50−0.5−1.0−1.5LARGE−SIGNALPULSERESPONSEG=+2V/VRL=150ΩVO=2VPPOutputVoltage(50mV/div)Time(10ns/div)REQUIREDRSvsCAPACITIVELOAD1dBPeakingTargetedNormalizedGaintoCapacitiveLoad(dB)40353025RS(Ω)2015105010100CapacitiveLoad(pF)1k3FREQUENCYRESPONSEvsCAPACITIVELOADCL=10pF0−3−6CL=100pF−9VIOPA832RSCL1kΩ(1)CL=1000pF−12−151NOTE: (1) 1kΩ is optional.10Frequency(MHz)1004006OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004TYPICAL CHARACTERISTICS: VS = ±5V (continued)At TA = 25°C, G = +2, and RL = 150Ω to GND, unless otherwise noted (see Figure 3).HARMONICDISTORTIONvsLOADRESISTANCE−40−50−602nd−Harmonic−703rd−Harmonic−80−90G=+2V/VVO=2VPPf=5MHz−50−60−70HARMONICDISTORTIONvsOUTPUTVOLTAGEG=+2V/VRL=500Ωf=5MHzHarmonicDistortion(dBc)HarmonicDistortion(dBc)3rd−Harmonic−802nd−Harmonic−90−100100LoadResistance(Ω)1k0123456710OutputSwing(VPP)HARMONICDISTORTIONvsFREQUENCY−40−50−60−70−803rd−Harmonic−90−100−1100.11Frequency(MHz)1020G=+2V/VRL=500ΩVO=2VPP−403rd−OrderSpuriousLevel(dBc)−45−50−55−60−65−70−75−80−85−90−26−22PITWO−TONE,3RD−ORDERINTERMODULATIONSPURIOUS50ΩOPA832500Ω400ΩPOHarmonicDistortion(dBc)2nd−Harmonic400Ω20MHz10MHz5MHz−18−14−10−6−226Single−ToneLoadPower(2dBm/div)OUTPUTVOLTAGEANDCURRENTLIMITATIONS63VO(V)210−1−2−3−4−5−6−160OutputCurrentLimit1WInternalPowerLimit1WInternalPowerLimitOUTPUTSWINGvsLOADRESISTANCE5MaximumOutputVoltage(V)43210−1−2−3−4−510100RL(Ω)1kG=+2V/VVS=±5VOutputCurrentLimitRL=500ΩRL=50ΩRL=100Ω−120−80−400IO(mA)40801201607OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004TYPICAL CHARACTERISTICS: VS = +5VAt TA = 25°C, G = +2, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 1).SMALL−SIGNALFREQUENCYRESPONSE30NormalizedGain(dB)−3−6−9−12−15110Frequency(MHz)100400G=+2VO=0.2VPPRL=150ΩNormalizedGain(dB)30−3−6−9−12−151LARGE−SIGNALFREQUENCYRESPONSERL=150ΩG=+2VPPVO=2VPPVO=1VPPG=−1VO=0.5VPP10Frequency(MHz)100400SMALL−SIGNALPULSERESPONSE0.150.100.050−0.05−0.10−0.15Time(10ns/div)G=+2V/VRL=150ΩVO=0.2VPP1.5OutputVoltage(500mV/div)1.00.50−0.5−1.0−1.5LARGE−SIGNALPULSERESPONSEG=+2V/VRL=150ΩVO=2VPPOutputVoltage(50mV/div)Time(10ns/div)REQUIREDRSvsCAPACITIVELOAD1dBPeakingTargetedNormalizedGaintoCapacitiveLoad(dB)403530RS(Ω)252015105010100CapacitiveLoad(pF)1k3FREQUENCYRESPONSEvsCAPACITIVELOADCL=10pF0−3−6−9−12−15−181NOTE: (1) 1kΩ is optional.VICL=1000pFCL=100pFRSCL1kΩ(1)10Frequency(MHz)1003008OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004TYPICAL CHARACTERISTICS: VS = +5V (continued)At TA = 25°C, G = +2, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 1).HARMONICDISTORTIONvsLOADRESISTANCE−40−50−602nd−Harmonic−70−80−903rd−HarmonicG=+2V/VVO=2VPPf=5MHz−40−50−60−70−80−90G=+2,HARMONICDISTORTIONvsFREQUENCYG=+2V/VRL=500ΩVO=2VPP2nd−HarmonicHarmonicDistortion(dBc)HarmonicDistortion(dBc)3rd−Harmonic−100−110100LoadResistance(Ω)1k0.11Frequency(MHz)1020HARMONICDISTORTIONvsOUTPUTVOLTAGE−40−50−60−70−80−90−1000.51.01.52.02.53.03..04.5OutputVoltageSwing(VPP)3rd−Harmonic2nd−HarmonicG=+2V/VRL=500Ωf=5MHzHarmonicDistortion(dBc)−30−40−50−60−70−80−90−100−1100.1G=−1,HARMONICDISTORTIONvsFREQUENCYG=−1V/VRL=500Ωf=5MHzHarmonicDistortion(dBc)3rd−Harmonic2nd−Harmonic1Frequency(MHz)1020−403rd−OrderSpuriousLevel(dBc)−45−50−55−60−65−70−75−80−85−90PI50ΩTWO−TONE,3RD−ORDERINTERMODULATIONSPURIOUSINPUTVOLTAGEANDCURRENTNOISE100InputVoltageNoise(nV/√Hz)InputCurrentNoise(pA/√Hz)OPA832500ΩPO10VoltageNoise(9.3nV/√Hz)20MHz10MHz5MHz−24−22−20−18−16−14−12−10−8Single−ToneLoadPower(dBm)−6−4−2CurrentNoise(2.3nV/√Hz)11001k10k100k1M10MFrequency(Hz)9OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004TYPICAL CHARACTERISTICS: VS = +5V (continued)At TA = 25°C, G = +2, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 1).COMMON−MODEREJECTIONRATIOANDPOWER−SUPPLYREJECTIONRATIOvsFREQUENCY8070PSRRandCMRR(dB)60+PSRRdG/dP504030201001001k10k100kFrequency(Hz)1M10M100MCOMPOSITEVIDEOdG/dP1.2+5V1.0CMRR0.8VIOPA832VideoLoadsdP0.60.40.201234Numberof150ΩLoadsdGOUTPUTSWINGvsLOADRESISTANCE5.04.5MaximumOutputVoltage(V)4.03.53.02.52.01.51.00.5010100RL(Ω)1kG=+2V/VVS=+5VOutputImpedance(Ω)CLOSED−LOOPOUTPUTIMPEDANCEvsFREQUENCY100400Ω+5V400Ω10OPA832ZO1200Ω0.11k10k100k1M10M100MFrequency(Hz)VOLTAGERANGESvsTEMPERATURE5.04..0VoltageRanges(V)3.53.02.52.01.51.00.50−0.5−1.0−5005090AmbientTemperature(10_C/div)LeastPositiveOutputVoltageLeastPositiveInputVoltageInputOffsetVoltage(mV)MostPositiveOutputVoltageMostPositiveInputVoltageRL=150Ω1.00.80.60.40.20−0.2−0.4−0.6−0.8−1.0−40TYPICALDCDRIFTOVERTEMPERATURE10BiasCurrent(IB)10×InputOffset(IOS)20−2InputOffsetVoltage(VOS)−4−6−8−20020406080100120−10130InputBiasandOffsetVoltage(µA)8AmbientTemperature(10_C/div)10OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004TYPICAL CHARACTERISTICS: VS = +5V (continued)At TA = 25°C, G = +2, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 1).SUPPLYANDOUTPUTCURRENTvsTEMPERATURE1009080OutputCurrent(mA)706050403020100−40−20020406080100120130QuiescentCurrentOutputCurrent,SinkingOutputCurrent,Sourcing7.57.06.56.05.55.04..03.53.02.5SupplyCurrent(mA)AmbientTemperature(_C/div)11OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004TYPICAL CHARACTERISTICS: VS = +3.3VAt TA = 25°C, G = +2, and RL = 150Ω to VCM = 0.75V, unless otherwise noted (see Figure 2).SMALL−SIGNALFREQUENCYRESPONSE30NormalizedGain(dB)−3G=+2−6−9−12−15110Frequency(MHz)100300VO=0.2VPPRL=150ΩNormalizedGain(dB)G=−130−3−6−9−12−151LARGE−SIGNALFREQUENCYRESPONSERL=150ΩG=+2V/VVO=1VPPVO=0.5VPPVO=2VPP10Frequency(MHz)100300SMALL−SIGNALPULSERESPONSE1.651.60OutputVoltage(V)1.551.501.451.401.35Time(10ns/div)G=+2V/VRL=150ΩVO=200mVPPOutputVoltage(V)2.11.91.71.51.31.10.9LARGE−SIGNALPULSERESPONSEG=+2V/VRL=150ΩVO=1VPPTime(10ns/div)REQUIREDRSvsCAPACITIVELOAD1dBPeakingTargetedNormalizedGaintoCapacitiveLoad(dB)605040RS(Ω)30201001101001kCapacitiveLoad(pF)3FREQUENCYRESPONSEvsCAPACITIVELOADCL=10pF0−3−6CL=100pF−9−12−15110Frequency(MHz)100300CL=1000pF12OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004TYPICAL CHARACTERISTICS: VS = +3.3V (continued)At TA = 25°C, G = +2, and RL = 150Ω to VCM = 0.75V, unless otherwise noted (see Figure 2).HARMONICDISTORTIONvsLOADRESISTANCE−50−55−603rd−Harmonic−65−70−75−80100LoadResistance(Ω)1k2nd−HarmonicG=+2V/VVO=1VPPf=5MHzHARMONICDISTORTIONvsOUTPUTVOLTAGE−40−50−60−702nd−Harmonic−80−90−1000.500.751.001.251.50OutputVoltageSwing(V)G=+2V/VRL=500Ωf=5MHzHarmonicDistortion(dBc)HarmonicDistortion(dBc)3rd−HarmonicHARMONICDISTORTIONvsFREQUENCY−40−50−60−70−80−90−100−1100.11Frequency(MHz)10203rd−Harmonic2nd−HarmonicG=+2V/VRL=500ΩVO=1VPP−403rd−OrderSpuriousLevel(dBc)−45−50−55−60−65−70−75−80−85−90−26−24PITWO−TONE,3RD−ORDERINTERMODULATIONSPURIOUSHarmonicDistortion(dBc)50ΩOPA832500ΩPO20MHz10MHz5MHz−22−20−18−16−14−12−10−8Single−ToneLoadPower(dBm)OUTPUTSWINGvsLOADRESISTANCE3.33.0MaximumOutputVoltage(V)2.72.42.11.81.51.20.90.60.3010G=+2V/VVS=+3.3VMostPositiveOutputVoltageLeastPositiveOutputVoltage100RL(Ω)1k13OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004APPLICATIONS INFORMATIONWIDEBAND VOLTAGE-FEEDBACKOPERATIONThe OPA832 is a fixed-gain, high-speed, voltage-feedback op amp designed for single-supply operation(+3V to +10V). It features internal RF and RG resistorswhich make it easy to select a gain of +2, +1, and −1without external resistors.The input stage supports inputvoltages below ground and to within 1.7V of the positivesupply. The complementary common-emitter output stageprovides an output swing to within 25mV of either supplypin. The OPA832 is compensated to provide stableoperation with a wide range of resistive loads.Figure 1 shows the AC-coupled, gain of +2 configurationused for the +5V Specifications and Typical CharacteristicCurves. The input impedance matching resistor (66.5Ω)used for testing is adjusted to give a 50Ω input match whenthe parallel combination of the biasing divider network isincluded. Voltage swings reported in the ElectricalCharacteristics are taken directly at the input and outputpins. For the circuit of Figure 1, the total effective load onthe output at high frequencies is 150Ω||800Ω. The 332Ωand 499Ω resistors at the noninverting input provide thecommon-mode bias voltage. Their parallel combinationequals the DC resistance at the inverting input (RF RG),reducing the DC output offset due to input bias current.Electrical Characteristics are taken directly at the inputand output pins. For the circuit of Figure 2, the totaleffective load on the output at high frequencies is150Ω||800Ω. The 887Ω and 258Ω resistors at thenoninverting input provide the common-mode biasvoltage. Their parallel combination equals the DCresistance at the inverting input (RF RG), reducing theDC output offset due to input bias current.VS=+3.3V6.8µF+887Ω0.1µF0.1µFVIN66.5ΩVCM=0.75V258ΩOPA832VOUTRL150ΩRG400ΩRF400ΩVCM=0.75VVCM=0.75VFigure 2. AC-Coupled, G = +2, +3.3VSingle-Supply Specification and Test CircuitVS=+5V6.8µF+499Ω0.1µF0.1µFVIN66.5ΩVCM=2V332ΩVOUTRL150ΩRG400ΩRF400ΩVCM=2VOPA832VCM=2VFigure 1. AC-Coupled, G = +2, +5V Single-SupplySpecification and Test CircuitFigure 2 shows the AC-coupled, gain of +2 configurationused for the +3.3V Specifications and TypicalCharacteristic Curves. The input impedance matchingresistor (66.5Ω) used for testing is adjusted to give a 50Ωinput match when the parallel combination of the biasingdivider network is included. Voltage swings reported in the14Figure 3 shows the DC-coupled, gain of +2, dualpower-supply circuit configuration used as the basis of the±5V Electrical Characteristics and Typical Characteristics.For test purposes, the input impedance is set to 50Ω witha resistor to ground and the output impedance is set to 50Ωwith a series output resistor. Voltage swings reported in thespecifications are taken directly at the input and outputpins. For the circuit of Figure 3, the total effective load willbe 150Ω || 800Ω. Two optional components are includedin Figure 3. An additional resistor (175Ω) is included inseries with the noninverting input. Combined with the 25ΩDC source resistance looking back towards the signalgenerator, this gives an input bias current cancellingresistance that matches the 200Ω source resistance seenat the inverting input (see the DC Accuracy and OffsetControl section). In addition to the usual power-supplydecoupling capacitors to ground, a 0.01µF capacitor isincluded between the two power-supply pins. In practicalPC board layouts, this optionally-added capacitor willtypically improve the 2nd-harmonic distortion performanceby 3dB to 6dB.OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004+5V0.1µF6.8µF+transient steps, DC performance, and noise under a widevariety of operating conditions. The models include thenoise terms found in the electrical specifications of thedata sheet. These models do not attempt to distinguishbetween the package types in their small-signal ACperformance.50ΩSource175ΩVIN50Ω0.01µFGAIN OF +2V/V VIDEO LINE DRIVEROPA832150ΩRF400ΩRG400Ω+−5V6.8µF0.1µFVideoIn+5VVOUTOne of the most suitable applicarions for the OPA832 is asimple gain of 2 video line driver. Figure 4 shows howsimple this circuit is to implement, shown as a ±5Vimplementation. Single +5V operation is similar withblocking caps and DC common-mode biasing provided.OPA832VideoLoadsOptional1.3kΩPull−DownFigure 3. DC-Coupled, G = +2, Bipolar SupplySpecification and Test Circuit−5VDESIGN-IN TOOLSDEMONSTRATION BOARDSSeveral PC boards are available to assist in the initialevaluation of circuit performance using the OPA832 in itstwo package styles. All of these are available, free, asunpopulated PC boards delivered with descriptivedocumentation. The summary information for theseboards is shown in Table 1.Figure 4. Gain of 2 Video Line DriverOne optional element is shown in Figure 4. A 1.3kΩpull-down to the negative supply will improve thedifferential phase significantly and the differential gainslightly. Figure 5 shows measured dG/dP with and withoutthat pull-down resistor from 1 to 4 video loads.Table 1. Demo Board AvailabilityPRODUCTOPA832IDOPA832IDBVPACKAGESO-8SOT23-5DEMO BOARDNUMBERDEM-OPA68xUDEM-OPA6xxNORDERINGNUMBERSBOU009dG/dP1.2+5V1.00.80.6VideoInOPA832VideoLoadsOptional1.3kΩPull−DownSBOU010−5VdP0.4dPdGGo to the TI web site (www.ti.com) to request evaluationboards through the OPA832 product folder.0.2dG0NoPull−DownWith1.3kΩPull−Down34MACROMODEL AND APPLICATIONSSUPPORTComputer simulation of circuit performance using SPICEis often a quick way to analyze the performance of theOPA832 and its circuit designs. This is particularly true forvideo and RF amplifier circuits where parasiticcapacitance and inductance can play a major role oncircuit performance. A SPICE model for the OPA832 isavailable through the TI web page (www.ti.com). Theapplications department is also available for designassistance. These models predict typical small signal AC,12Numberof150ΩLoadsFigure 5. dG/dP vs Video Loads15OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004SINGLE-SUPPLY ADC INTERFACEThe circuit shown in Figure 6 uses the OPA832 as adifferential driver followed by an RC filter. In this circuit, thesingle-ended to differential conversion is realized by a 1:1transformer driving the noninverting inputs of the twoOPA832s. The common-mode level (CML) of theADS5203 is reduced to the appropriate input level of0.885V by the network divider composed of R1 and theCML output impedance, and connected to the transformercenter tap, biasing the OPA832s. This input bias voltageis then amplified to provide the correct common-modevoltage to the input of the ADC. Using only 25.1mW power(3.8mA × 2 amplifiers × 3.3V), this configuration (amplifier+ ADC) provides greater than 59dB SNR and 70dB SFDRto 2MHz, with all the components running on a low +3.3Vsupply.+3.3VRT20ΩOPA832RS50Ω+3.3VINVIN50ΩSource1:1RM50ΩRG400ΩRF400ΩC15pF1/2ADS520310−Bit40MSPS+3.3VRT20ΩOPA832RS50ΩINCML2.3kΩOutputImpedanceVCM=0.885VRI1.91kΩC10.1µFRG400ΩRF400ΩFigure 6. Low-Power, Single-Supply ADC Driver16OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004This circuit removes the peaking by bootstrapping out anyparasitic effects on RG. The input impedance is still set byRM as the apparent impedance looking into RG is veryhigh. RM may be increased to show a higher inputimpedance, but larger values will start to impact DC outputoffset voltage. This circuit creates an additional input offsetvoltage as the difference in the two input bias current timesthe impedance to ground at VIN. Figure 8 shows acomparison of small-signal frequency response for theunity-gain buffer of Figure 2 (with VCM removed from RG)compared to the improved approach shown in Figure 7.OPERATING SUGGESTIONSGAIN SETTINGSetting the gain for the OPA832 is very easy. For a gain of+2, ground the −IN pin and drive the +IN pin with the signal.For a gain of +1, either leave the −IN pin open and drive the+IN pin or drive both the +IN and −IN pins as shown inFigure 7. For a gain of −1, ground the +IN pin and drive the−IN pin with the input signal. An external resistor may beused in series with the −IN pin to reduce the gain. However,since the internal resistors (RF and RG) have a toleranceand temperature drift different than the external resistor,the absolute gain accuracy and gain drift over temperaturewill be relatively poor compared to the previouslydescribed standard gain connections using no externalresistor.+5VRO75ΩOPA832VOUTOUTPUT CURRENT AND VOLTAGESThe OPA832 provides outstanding output voltagecapability. Under no-load conditions at +25°C, the outputvoltage typically swings closer than 90mV to either supplyrail.The minimum specified output voltage and currentspecifications over temperature are set by worst-casesimulations at the cold temperature extreme. Only at coldstartup will the output current and voltage decrease to thenumbers shown in the min/max tables. As the outputtransistors deliver power, their junction temperatures willincrease, decreasing their VBEs (increasing the availableoutput voltage swing) and increasing their current gains(increasing the available output current). In steady-stateoperation, the available output voltage and current willalways be greater than that shown in the over-temperaturespecifications, since the output stage junctiontemperatures will be higher than the minimum specifiedoperating ambient.To maintain maximum output stage linearity, no outputshort-circuit protection is provided. This will not normallybe a problem, since most applications include a seriesmatching resistor at the output that will limit the internalpower dissipation if the output side of this resistor isshorted to ground. However, shorting the output pindirectly to the adjacent positive power-supply pin (8-pinpackages) will possibly destroy the amplifier. If additionalshort-circuit protection is required, consider a small seriesresistor in the power-supply leads. This will reduce theavailable output voltage swing under heavy output loads.RG400ΩVINRM50ΩRF400ΩFigure 7. Improved Unity-Gain BufferUNITY-GAIN BUFFERThis buffer can simply be realized by not connecting RG toground. This type of realization shows a peaking in thefrequency response. A similar circuit that holds a flatfrequency response giving improved pulse fidelity isshown in Figure 7.630Gain(dB)−3−6−9−12110Frequency(MHz)100400G=+1BufferFigure5G=+1BufferRGFloatingDRIVING CAPACITIVE LOADSOne of the most demanding and yet very common loadconditions for an op amp is capacitive loading. Often, thecapacitive load is the input of an ADC—includingadditional external capacitance which may be recom-mended to improve ADC linearity. A high-speed, highopen-loop gain amplifier like the OPA832 can be verysusceptible to decreased stability and closed-loopresponse peaking when a capacitive load is placed directlyon the output pin. When the primary considerations arefrequency response flatness, pulse response fidelity,17Figure 8. Buffer Frequency ResponseComparisonOPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004and/or distortion, the simplest and most effective solutionis to isolate the capacitive load from the feedback loop byinserting a series isolation resistor between the amplifieroutput and the capacitive load.The Typical Characteristic curves show the recommendedRS versus capacitive load and the resulting frequencyresponse at the load. Parasitic capacitive loads greaterthan 2pF can begin to degrade the performance of theOPA832. Long PC board traces, unmatched cables, andconnections to multiple devices can easily exceed thisvalue. Always consider this effect carefully, and add therecommended series resistor as close as possible to theoutput pin (see the Board Layout Guidelines section).The criterion for setting this RS resistor is a 1dB peakedfrequency response at the load. Increasing the noise gainwill also reduce the peaking (see Figure 7).NOISE PERFORMANCEUnity-gain stable, rail-to-rail (RR) output, voltage-feed-back op amps usually show a higher input noise voltage.The 9.2nV/√Hz input voltage noise for the OPA832however, is much lower than comparable amplifiers. Theinput-referred voltage noise and the two input-referredcurrent noise terms (2.8pA/√Hz) combine to give lowoutput noise under a wide variety of operating conditions.Figure 10 shows the op amp noise analysis model with allthe noise terms included. In this model, all noise terms aretaken to be noise voltage or current density terms in eithernV/√Hz or pA/√Hz.ENIDISTORTION PERFORMANCEThe OPA832 provides good distortion performance into a150Ω load. Relative to alternative solutions, it providesexceptional performance into lighter loads and/oroperating on a single +3.3V supply. Generally, until thefundamental signal reaches very high frequency or powerlevels, the 2nd-harmonic will dominate the distortion witha negligible 3rd-harmonic component. Focusing then onthe 2nd-harmonic, increasing the load impedanceimproves distortion directly. Remember that the total loadincludes the feedback network; in the noninvertingconfiguration (see Figure 3) this is sum of RF + RG, whilein the inverting configuration, only RF needs to be includedin parallel with the actual load.Figure 9 shows the 2nd- and 3rd-harmonic distortionversus supply voltage. In order to maintain the input signalwithin acceptable operating range, the inputcommon-mode voltage is adjusted for each supplyvoltage. For example, the common-mode voltage is +2Vfor a single +5V supply, and the distortion is −66.5dBc forthe 2nd-harmonic and −74.6dBc for the 3rd-harmonic.RSOPA832IBNEOERS√4kTRSRF√4kTRF4kT=1.6E−20Jat290_K4kTRGRGIBIFigure 10. Noise Analysis ModelThe total output spot noise voltage can be computed as thesquare root of the sum of all squared output noise voltagecontributors. Equation 1 shows the general form for theoutput noise voltage using the terms shown in Figure 10:EO+ǸǒENI)ǒIBNRSǓ)4kTRSNG2)ǒIBIRFǓ)4kTRFNG222Ǔ−66−67HarmonicDistortion(dBc)−68−69−70−71−72−73−74−75−7652nd−HarmonicLeftScale4..03.53.02.5G=+2V/VRL=500ΩVO=2VPPf=5MHz10112.01.51.00.5Common−ModeVoltage(V)Common−ModeVoltageRightScale5.55.0(1)Dividing this expression by the noise gain(NG=(1+RF/RG)) will give the equivalent input-referredspot noise voltage at the noninverting input, as shown inEquation 2:EN+ǸENI)ǒIBNRSǓ22IR)4kTRS)BIFNGǒǓ2)4kTRFNG3rd−HarmonicLeftScale67(2)SupplyVoltage(V)Figure 9. 5MHz Harmonic Distortion vs SupplyVoltageEvaluating these two equations for the circuit andcomponent values shown in Figure 1 will give a total outputspot noise voltage of 19.3nV/√Hz and a total equivalentinput spot noise voltage of 9.65nV/√Hz. This is includingthe noise added by the resistors. This total input-referredspot noise voltage is not much higher than the 9.2nV/√Hzspecification for the op amp voltage noise alone.18OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004DC ACCURACY AND OFFSET CONTROLThe balanced input stage of a wideband voltage-feedbackop amp allows good output DC accuracy in a wide varietyof applications. The power-supply current trim for theOPA832 gives even tighter control than comparableproducts. Although the high-speed input stage doesrequire relatively high input bias current (typically 5µA outof each input terminal), the close matching between themmay be used to reduce the output DC error caused by thiscurrent. This is done by matching the DC sourceresistances appearing at the two inputs. Evaluating theconfiguration of Figure 3 (which has matched DC inputresistances), using worst-case +25°C input offset voltageand current specifications, gives a worst-case outputoffset voltage equal to:Note that it is the power in the output stage, and not into theload, that determines internal power dissipation.As a worst-case example, compute the maximum TJ usingan OPA832 (SOT23-5 package) in the circuit of Figure 3operating at the maximum specified ambient temperatureof +85°C and driving a 150Ω load at mid-supply.PD = 10V × 3.9mA + 52/(16 × (150Ω || 400Ω)) = 53.3mWMaximum TJ = +85°C + (0.053W × 150°C/W) = 93°C.(NG = noninverting signal gain at DC)±(NG × VOS(MAX)) ± (RF × IOS(MAX))= ±(2 × 10mV) ± (400Ω × 1.5µA)= ±10.6mVA fine-scale output offset null, or DC operating pointadjustment, is often required. Numerous techniques areavailable for introducing DC offset control into an op ampcircuit. Most of these techniques are based on adding a DCcurrent through the feedback resistor. In selecting an offsettrim method, one key consideration is the impact on thedesired signal path frequency response. If the signal pathis intended to be noninverting, the offset control is bestapplied as an inverting summing signal to avoid interactionwith the signal source. If the signal path is intended to beinverting, applying the offset control to the noninvertinginput may be considered. Bring the DC offsetting currentinto the inverting input node through resistor values thatare much larger than the signal path resistors. This willinsure that the adjustment circuit has minimal effect on theloop gain and hence the frequency response.Although this is still well below the specified maximumjunction temperature, system reliability considerationsmay require lower ensured junction temperatures. Thehighest possible internal dissipation will occur if the loadrequires current to be forced into the output at high outputvoltages or sourced from the output at low output voltages.This puts a high current through a large internal voltagedrop in the output transistors.BOARD LAYOUT GUIDELINESAchieving optimum performance with a high-frequencyamplifier like the OPA832 requires careful attention toboard layout parasitics and external component types.Recommendations that will optimize performance include:a) Minimize parasitic capacitance to any AC ground forall of the signal I/O pins. Parasitic capacitance on theoutput and inverting input pins can cause instability: on thenoninverting input, it can react with the source impedanceto cause unintentional bandlimiting. To reduce unwantedcapacitance, a window around the signal I/O pins shouldbe opened in all of the ground and power planes aroundthose pins. Otherwise, ground and power planes shouldbe unbroken elsewhere on the board.b) Minimize the distance ( < 0.25”) from the power-supplypins to high-frequency 0.1µF decoupling capacitors. At thedevice pins, the ground and power-plane layout should notbe in close proximity to the signal I/O pins. Avoid narrowpower and ground traces to minimize inductance betweenthe pins and the decoupling capacitors. Each power-supply connection should always be decoupled with oneof these capacitors. An optional supply decouplingcapacitor (0.1µF) across the two power supplies (forbipolar operation) will improve 2nd-harmonic distortionperformance. Larger (2.2µF to 6.8µF) decouplingcapacitors, effective at lower frequency, should also beused on the main supply pins. These may be placedsomewhat farther from the device and may be sharedamong several devices in the same area of the PC board.c) Careful selection and placement of externalcomponents will preserve the high-frequency perfor-mance. Resistors should be a very low reactance type.Surface-mount resistors work best and allow a tighteroverall layout. Metal film or carbon compositionaxially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC19THERMAL ANALYSISMaximum desired junction temperature will set themaximum allowed internal power dissipation, asdescribed below. In no case should the maximum junctiontemperature be allowed to exceed 150°C.Operating junction temperature (TJ) is given byTA+PD×qJA. The total internal power dissipation (PD)is the sum of quiescent power (PDQ) and additionalpower dissipated in the output stage (PDL) to deliver loadpower. Quiescent power is simply the specified no-loadsupply current times the total supply voltage across thepart. PDL will depend on the required output signal andload; though, for resistive loads connected tomid-supply (VS/2), PDL is at a maximum when the outputis fixed at a voltage equal to VS/4 or 3VS/4. Under thiscondition, PDL=VS2/(16×RL), where RL includesfeedback network loading.OPA832www.ti.comSBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004board traces as short as possible. Never use wire-woundtype resistors in a high-frequency application. Since theoutput pin is the most sensitive to parasitic capacitance,always position the series output resistor, if any, as closeas possible to the output pin. Other network components,such as noninverting input termination resistors, shouldalso be placed close to the package.d) Connections to other wideband devices on the boardmay be made with short direct traces or through onboardtransmission lines. For short connections, consider thetrace and the input to the next device as a lumpedcapacitive load. Relatively wide traces (50mils to 100mils)should be used, preferably with ground and power planesopened up around them. Estimate the total capacitive loadand set RS from the typical characteristic curveRecommended RS vs Capacitive Load. Low parasiticcapacitive loads (< 5pF) may not need an RS since theOPA832 is nominally compensated to operate with a 2pFparasitic load. Higher parasitic capacitive loads without anRS are allowed as the signal gain increases (increasing theunloaded phase margin). If a long trace is required, and the6dB signal loss intrinsic to a doubly-terminatedtransmission line is acceptable, implement a matchedimpedance transmission line using microstrip or striplinetechniques (consult an ECL design handbook formicrostrip and stripline layout techniques). A 50Ωenvironment is normally not necessary onboard, and infact, a higher impedance environment will improvedistortion as shown in the distortion versus load plots. Witha characteristic board trace impedance defined (based onboard material and trace dimensions), a matching seriesresistor into the trace from the output of the OPA832 isused as well as a terminating shunt resistor at the input ofthe destination device. Remember also that theterminating impedance will be the parallel combination ofthe shunt resistor and the input impedance of thedestination device; this total effective impedance shouldbe set to match the trace impedance. If the 6dB attenuationof a doubly-terminated transmission line is unacceptable,a long trace can be series-terminated at the source endonly. Treat the trace as a capacitive load in this case andset the series resistor value as shown in the typicalcharacteristic curve Recommended RS vs CapacitiveLoad. This will not preserve signal integrity as well as adoubly-terminated line. If the input impedance of thedestination device is low, there will be some signalattenuation due to the voltage divider formed by the seriesoutput into the terminating impedance.e) Socketing a high-speed part is not recommended.The additional lead length and pin-to-pin capacitanceintroduced by the socket can create an extremelytroublesome parasitic network which can make it almostimpossible to achieve a smooth, stable frequencyresponse. Best results are obtained by soldering theOPA832 onto the board.INPUT AND ESD PROTECTIONThe OPA832 is built using a very high-speed complemen-tary bipolar process. The internal junction breakdownvoltages are relatively low for these very small geometrydevices. These breakdowns are reflected in the AbsoluteMaximum Ratings table. All device pins are protectedwith internal ESD protection diodes to the power supplies,as shown in Figure 11.+VCCExternalPinInternalCircuitry−VCCFigure 11. Internal ESD ProtectionThese diodes provide moderate protection to inputoverdrive voltages above the supplies as well. Theprotection diodes can typically support 30mA continuouscurrent. Where higher currents are possible (that is, insystems with ±15V supply parts driving into the OPA832),current-limiting series resistors should be added into thetwo inputs. Keep these resistor values as low as possible,since high values degrade both noise performance andfrequency response.20PACKAGEOPTIONADDENDUMwww.ti.com15−Sep−2004PACKAGINGINFORMATIONORDERABLEDEVICEOPA832IDOPA832IDROPA832DBVTOPA832DBVRSTATUS(1)ACTIVEACTIVEACTIVEACTIVEPACKAGETYPESO−8SO−8SOT23SOT23PACKAGEDRAWINGDDDBVDBVPINS8855PACKAGEQTY10025002503000ECO−STATUS(2)N/AN/APb−Free,GreenPb−Free,Green(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime−buyperiodisineffect.NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.(2)Eco−StatusinformationAdditionaldetailsincludingspecificmaterialcontentcanbeaccessedatwww.ti.com/leadfreeGREEN:TidefinesGreentomeanLead(Pb)−Freeandinaddition,useslesspackagematerialsthatdonotcontainhalogens,includingbromine(Br),orantimony(Sb)above0.1%oftotalproductweight.N/A:NotyetavailableLead(Pb)−Free;forestimatedconversiondates,gotowww.ti.com/leadfree.Pb−FREE:TidefinesLead(Pb)−FreetomeanRoHScompatible,includingaleadconcentrationthatdoesnotexceed0.1%oftotalproductweight,and,ifdesignedtobesoldered,suitableforuseinspecifiedlead−freesolderingprocesses.IMPORTANT NOTICE
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